Part Number S2004
Revision J – April 7, 2006
S2004
Quad Serial Backplane Device
FEATURES
•
Broad operating rate range (.98 - 1.3 GHz)
- 1062 MHz (Fibre Channel)
- 531.5 MHz Half Rate Operation
- 1250 MHz (Gigabit Ethernet) line rates
- 625 MHz Half Rate Operation
Quad Transmitter with phase-locked loop (PLL)
clock synthesis from low speed reference
Quad Receiver PLL provides clock and data
recovery
Internally series terminated TTL outputs
On-chip 8B/10B line encoding and decoding
for four separate parallel 8-bit channels
32-bit parallel TTL interface with internal series
terminated outputs
Low-jitter serial PECL interface
Individual local loopback control
JTAG 1149.1 Boundary scan on low speed I/O
signals
Interfaces with coax, twinax, or fiber optics
Single +3.3V supply, 2.5 W power dissipation
Compact 23mm x 23mm 208 TBGA package
with Green/RoHS compliant lead free option
•
•
Data Sheet
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2004 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, Fibre Channel, serial backplanes, and pro-
prietary point to point links. The chip provides four
separate transceivers which can be operated individu-
ally or locked together for an aggregate data capacity
of >4 Gbps.
Each bi-directional channel provides 8B/10B coding/
decoding, parallel to serial and serial to parallel con-
version, clock generation/recovery, and framing. The
on-chip transmit PLL synthesizes the high-speed clock
from a low-speed reference. The on-chip quad receive
PLL is used for clock recovery and data re-timing on
the four independent data inputs. The transmitter and
receiver each support differential PECL-compatible I/O
for copper or fiber optic component interfaces with
excellent signal integrity. Local loopback mode allows
for system diagnostics. The chip requires a 3.3V
power supply and dissipates 2.5 watts.
Ethernet application. Figure 2 combines the S2004
with a crosspoint switch to demonstrate a serial back-
plane application.Figure 3 is the input/output diagram.
block diagrams, respectively.
•
•
•
•
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
Ethernet Backbones
Workstation & Frame buffers
Switched networks
Figure 1. Typical Quad Gigabit Ethernet Application
GE INTERFACE
SERIAL BP DRIVER
MAC
(ASIC)
QUAD
GIGABIT
ETHERNET
INTERFACE
MAC
(ASIC)
TO SERIAL BACKPLANE
S2204
MAC
(ASIC)
S2004
MAC
(ASIC)
AMCC Confidential and Proprietary
1
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
