Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
Table 16. Recommended Operating Conditions
The device will meet all electrical specifications at a junction temperature under bias of 125C but part lifetime and reliability may be reduced. It
is recommended that prudent thermal management techniques are used to maximize device lifetime.
Output Mode
Parameter
Ambient Temperature Under Bias
Min
Typ
Max
85
Units
°C
-40
Junction Temperature Under Bias
125
1.26
°C
Voltage on VDD with Respect to GND
1.2 V Operation
1.14
3.135
0
1.2
3.3
V
Voltage on VDD with Respect to GND
3.3 V Operation
3.465
V
V
Voltage on any LVCMOS Input Pin
VDDH
IO
3.3 V LVPECL Power Dissipation when VDDH=3.3V and SERCLKOOFF=0, TSCLK-
840
900
775
830
620
650
1065
1165
960
mW
No TSCLK
OOFF=1, XLVDSPECLB=0. All 4 channels used.
For current consumption see Table 17.
3.3 V LVPECL Power Dissipation when VDDH=3.3V and SERCLKOOFF=0, TSCLK-
mW
mW
mW
mW
mW
with TSCLK
OOFF=0, XLVDSPECLB=0. All 4 channels used. For current consump-
tion see Table 17.
3.3 V LVDS
No TSCLK
Power Dissipation when VDDH=3.3V and SERCLKOOFF=0, TSCLK-
OOFF=1, XLVDSPECLB=1. All 4 channels used. For current consump-
tion see Table 17.
3.3 V LVDS
With TSCLK
Power Dissipation when VDDH=3.3V and SERCLKOOFF=0, TSCLK-
OOFF=0, XLVDSPECLB=1. All 4 channels used. For current consump-
tion see Table 17.
1055
745
2.5 V LVDS
No TSCLK
Power Dissipation when VDDH=2.5 V and SERCLKOOFF=0, TSCLK-
OOFF=1, XLVDSPECLB=1. All 4 channels used. For current consump-
tion see Table 17, on.
2.5 V LVDS
With TSCLK
Power Dissipation when VDDH=2.5 V and SERCLKOOFF=0, TSCLK-
OOFF=0, XLVDSPECLB=1. All 4 channels used. For current consump-
tion see Table 17.
795
Power supply noise tolerance for 1.2 V (6 kHz – 2 MHz)
Power supply noise tolerance for 2.5 V (6 kHz – 2 MHz)
Power supply noise tolerance for 3.3 V (6 kHz – 2 MHz)
50
50
50
mVp-p
mVp-p
mVp-p
See Note *
See Note *
Note: Channel not used (disabled) contributes no power dissipation. Reduce 25% of the power dissipation in the relevant row with TSCLKOOFF=1 for each dis-
abled channel.
* Noise on the power supply within the PLL bandwidth impacts the Jitter Generation performance.
30
DS2018
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