Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
PERFORMANCE SPECIFICATIONS
Table 14. Performance Specifications
Parameter
Min
Typ
Max
Units
Conditions
VCO Frequency
500
622.08
700
MHz
Valid for OC-3/OC-12.
Temperature
(°C)
Mode
REFCLK
(MHz)
155.52
77.76
0.002
0.002
0.002
0.003
0.003
0.007
0.002
0.002
0.002
0.003
0.003
0.007
0.005
0.006
0.005
0.006
0.005
0.005
0.005
0.005
0.005
0.010
0.005
0.005
0.005
0.006
0.006
0.011
0.007
0.008
0.008
0.009
STS-3
19.44
0 to 85
155.52
In Lock
Jitter
Generation
(CSU)
Jitter added to the REFCLK
input jitter.
In this measured bandwidth:
12 kHz -> 1.3 MHz (OC-3)
12 kHz -> 5 MHz (OC-12)
STS-12 77.76
19.44
UI
(rms)
TSCLKP/N
155.52
STS-3
77.76
19.44
155.52
-40 to 85
STS-12 77.76
19.44
STS-3
In Lock
Jitter added to the
0 to 85
STS-12
SERDATIP/N input jitter.
In this measured bandwidth:
12 kHz -> 1.3 MHz (OC-3)
12 kHz -> 5 MHz (OC-12)
All unused channels are
powered down, or locked to
reference or disabled by the
associated Signal
STS-3
Jitter
Generation
(CRU)
UI
(rms)
SERCLKOP/N
-40 to 85
STS-12
Detect(SD).
STS-3 and
STS-12
With respect to fixed refer-
ence frequency.
Lock Range
%
±
12
Capture Time
µs
Guaranteed by design but
not tested.
32
Acquisition Lock Time
500
732
ms
With device already pow-
ered up and valid reference
clock.
Valid for OC-3/OC-12.
Frequency difference at which PLL goes out of lock
(REFCLK compared to the divided down VCO clock).
340
ppm
Previously in lock.
Valid for OC-3/OC-12.
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DS2018
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
