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QT2032 参数 Datasheet PDF下载

QT2032图片预览
型号: QT2032
PDF下载: 下载PDF文件 查看货源
内容描述: [10 Gb/s Serial-to-XAUI PHY ICs for Ethernet and Fibre Channel LAN/ SAN/WAN Applications (CDR)]
分类和应用: 局域网
文件页数/大小: 220 页 / 2383 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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QT2022/32 - Data Sheet: DS3051  
Figure 30: QT2022/32 DOM Application Diagram  
3.3 V  
EEPROM_SDA  
EEPROM_SCL  
address  
1010000  
QT2032/  
QT2022  
EEPROM  
DOM  
device  
address  
1010xxx  
The EEPROM and DOM are at different device addresses.  
The current 256 NVR registers will continue to be read from an external EEPROM with device address 1010000.  
NVR register mapping and update control conform to the XENPAK MSA.  
MDIO device number 1 is used for the NVR registers and DOM registers on QT2022/32.  
The presence of an external DOM device is indicated by NVR register 1.807Ah.6. This bit must be set to 1 to  
enable the QT2022/32 DOM logic. The lower 3 bits of the DOM device address are read from NVR register  
1.807Ah.2:0 (defaults to 001 after reset). The upper 4 device address bits are hardwired to 1010. The DOM device  
address must be in the range 1010001x to 1010111x.  
The default frequency of the serial interface clock, EEPROM_SCL, is 37kHz. This will result in an upload time of  
approximately 62ms for 256 bytes assuming for no wait times for the DOM device to respond. Clock stretching is  
supported.  
Refer to Section 18.10, “DOM Memory Behavior,” on page 216 for details on DOM Memory usage.  
10.5.1 DOM Upload on Reset  
Both the NVR and DOM registers are set to their default values by a hardware or software reset. The NVR regis-  
ters are automatically uploaded after a reset is applied to the QT2022/32. The upload begins 250 ms after the reset  
function is completed. This delay is to allow the external devices time to stabilize after power up. After the NVR reg-  
isters are successfully uploaded, and if a DOM device is present, the DOM registers will be uploaded. The DOM  
update frequency defaults to a single upload (1.A100h.1:0=00). If a reset occurs in the middle of a DOM or  
EEPROM transaction, the transaction is stopped immediately, the QT2022/32 releases the EEPROM_SDA pin and  
drives the EEPROM_SCL pin high.  
The EEPROM and DOM upload sequence is presented in figure 36 on page 92.  
Revision 5.11  
AppliedMicro - Confidential & Proprietary  
85  
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