QT2022/32 - Data Sheet: DS3051
10.1.3 Acknowledge
The transmitting device releases the EEPROM_SDA line after transmitting eight data or address bits. During the
ninth cycle the receiving device will pull the EEPROM_SDA line low to acknowledge that it received the bits.
Figure 27: Acknowledge Condition
EEPROM_SDA
2 through 7
8
1
9
EEPROM_SCL
A
S
Acknowledge Condition
Start Condition
10.1.4 Bus Rate Control
The default clock rate for the EEPROM bus is 37kHz when the chip is the bus master. The QT2022/32’s master
bus rate can be increased to 74kHz or 600kHz using the bus rate control bits 1.C003h.15:14.
10.2 EEPROM 256 Byte Read Cycle
The EEPROM 256 Byte Read Cycle is initiated by setting the MDIO register bits 1.32768.0:1 and clearing bit
1.32768.5 (1.8000h.5). Bits 0 and 1 are self clearing after the EEPROM 256 Byte Read Cycle is complete. MDIO
registers 1.32768.3:2 (1.8000h.3:2) indicate when the read has been completed. The EEPROM command status
register must be in the idle state, 1.8000h.2:3=00, for an EEPROM read command to be accepted.
The completion of a hard reset via the RESETN pin or a software reset via the MDIO also triggers the 256 byte
read cycle. When powering up the QT2022/32, a hard reset will be applied, and the EEPROM registers will be
automatically uploaded. The upload is part of the initialization sequence for the QT2022/32 and must be completed
before the device is ready for use. The EEPROM command status register, MDIO 1.8000h.2:3, can be monitored
to see when the upload has been completed. A complete upload of 256 bytes requires approximately 60 ms, when
the burst read size is set to the default value of 256 bytes.
The timing for the 256 Byte Read Cycle is shown in the figure figure 28 on page 83. The EEPROM internal address
counter is first set to 0 by a dummy write cycle. This is followed by a random access read from word address 0. The
reception of the 8 data bits is followed by an acknowledgement (ACK) from the QT2022/32. The ACK indicates to
the EEPROM that data from the next word address will be read. An ACK is supplied after the reception of each
data byte until a total of 256 bytes have been read. No ACK is given after data byte 255 followed by a STOP (P) to
terminated the sequential read cycle.
The data which is read is stored in 256 MDIO registers starting at address 1.8007h through to address 1.8106h.
The 8 bit bytes from the EEPROM are mapped onto the 8 LSB’s of the associated MDIO register. The other 8 bits
are unused. They cannot be written to, and will return a value of 0 if read.
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