QT2022/32 - Data Sheet: DS3051
Figure 28: EEPROM 256 Byte Read Cycle Timing
address byte
00000000
data byte 255
data bytes 2 - 254
data byte 0
slave address
slave address
P
A
A
d7
d0
1
0
0
0
1
0
0
S
0
d7
S
0
0
A
0
0
0
0
1
d0
d6
d6
1
0
0
d7 d1
d6
d1
d1
d0
0
A
1
A
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
S
T
A
R
T
S
T
A
R
T
S
T
O
P
W
R
I
T
E
R
E
A
D
A
C
K
PHY
EEPROM
EEPROM address counter write = dummy write
random access read from word address 0
The MDIO interface transmits and receives bit 15 first. The EEPROM protocol has bit 7 transmitted first. MDIO data
bits are numbered from 0 to 15. EEPROM bits are numbered from 0 to 7. EEPROM bit 0 is mapped to MDIO regis-
ter bit 0, EEPROM bit 7 is mapped to MDIO register bit 7. The upper 8 MDIO register bits are hard wired to 0.
The EEPROM slave address is hard wired to 1010000. The first 4 bits of the slave address (1010) are the
EEPROM device type identifier portion and 000 is the EEPROM device address.
The EEPROM must provide an acknowledgement (ACK) when presented with its slave address before any reads
or writes can occur. Upon reception of the ACK, the sequential read can commence. The EEPROM must also pro-
vide an ACK after the address byte field and slave address field are sent. If any of the three expected ACKs is not
provided by the EEPROM, the QT2022/32 will restart the read cycle. If proper ACKs are not received after 16 poll-
ing sequences the error flag EEPROM_ACK_error is set and the read sequence is aborted. This error flag can be
accessed at MDIO register address 1.C003h.12. It is cleared upon a read of this register or a QT2022/32 chip
reset.
10.2.1 EEPROM Checksum Checking
The QT2022/32 will perform a checksum calculation and compare after every successful 256 byte read. The
checksum for comparison is in EEPROM register 118 = 1.32893 (1.807Dh). The checksum is equal to the 8 LSB’s
of the sum of bytes 0 to 117 of the EEPROM. The calculated checksum is stored in MDIO register 1.C004h.15:8.
The result of the comparison of the calculated checksum with the one read from the EEPROM is placed in MDIO
register 1.C003h.7.
10.3 EEPROM 256 Byte Write Cycle
An EEPROM 256 Byte Write Cycle is initiated by setting MDIO bits 1.8000h.0,1 and 5 to 1.
The EEPROM command status register must be in the idle state, 1.8000h.2:3=00, for an EEPROM write command
to be accepted.
The information to be written to the EEPROM is stored in the same 256 MDIO registers where the data read from
the EEPROM is placed. Data must be placed in MDIO registers 1.8007h to 1.8106h via the MDIO interface before
starting the EEPROM 256 byte write sequence.
Page write mode is used to transfer 1, 8 or 16 bytes (set by MDIO register 1.C003h.1:0) to the EEPROM at a time.
It is done sequentially 256, 32 or 16 times in order to transfer all 256 bytes. In between page writes, the QT2022/32
polls the EEPROM for an ACK, which indicates that the EEPROM internal write cycle is completed. If no ACK is
received, the QT2022/32 waits for 1.7ms and then repeats the poll for an ACK. After 16 tries without an ACK, the
write cycle is aborted and the EEPROM_ACK_error flag is set. An ACK must be received after each data word is
written or the write cycle is aborted and the EEPROM_ACK_error flag is set. MDIO registers 1.32768.3:2
(1.8000h.3:2) indicate when the write has been completed.
Revision 5.11
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