QT2022/32 - Data Sheet: DS3051
Table 34: XENPAK EEPROM Register Map (Continued)
MDIO register
EEPROM reg
address
bits7:0default
a
address
value
XENPAK MSA Description
:
255
FF
33030
8106
00
a
bits 15:8 of the MDIO registers are reserved (RO) and will return a value of 0 when read.
10.1 EEPROM Data Transfer Timing
10.1.1 Data Transfer
The data on the EEPROM_SDA line must be stable during the HIGH period of the clock EEPROM_SCL. The HIGH
or LOW state of the data line can only change when EEPROM_SCL is LOW.
Figure 25: Data Bit Transfer
EEPROM_SCL
EEPROM_SDA
change
data line stable
data valid
allowed
of data
10.1.2 Start and Stop Conditions
A HIGH to LOW transition on the EEPROM_SDA line while EEPROM_SCL is high defines a START condition. A
LOW to HIGH transition on the EEPROM_SDA line while EEPROM_SCL is high defines a STOP condition. START
and STOP conditions are generated by the bus master
Figure 26: Start and Stop Conditions
EEPROM_SDA
EEPROM_SCL
S
P
Stop Condition
Start Condition
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