QT2022/32 - Data Sheet: DS3051
Features
Benefits
Selectable LAN or WAN 1 mode operation
10GE, 10GFC and SONET 1 data rate support
Compliant to IEEE 802.3-2005 standard including WIS 1 , and
Single module footprint to support LAN and WAN.
Compliant with multiple protocols
Industry standard operation
XENPAK and XFP MSAs
Selectable XAUI lane ordering
Flexible system card design
Selectable 10G I/O polarity
Accommodates polarity inversion
Adjustable XAUI and 10G output amplitude
9.6kB jumbo frame support
Optimizes performance / power
Supports all Ethernet frame sizes
3.3V tolerant I/O
Optional ability to configure registers from an external EEPROM
on powerup or reset
Low speed I/O pins are compatible with 3.3V logic
Modify default register settings to customize device operation.
Configurable polarity of low-speed CMOS I/O
25MHz MDIO operation
Flexible interface logic
Superior bus speed
1. QT2032 only
QT2032 WIS Features
WIS interface with extended SONET overhead processing
SONET overhead serial interface
Line-timing capability with optional VCXO interface
Conditional (auto-linetiming) or forced line-timing operation
VCXOONLY mode where the local SONET reference clock is
eliminated
Maximum flexibility in network design
SONET overhead insertion and extraction
Support synchronous transport
Flexible operation
Reduce system cost
SONET-compliant jitter performance
Compatible with SONET network timing requirements
Module Features
Integrated limiting amplifier with 20mVppD sensitivity
Internal LOS detector with option to use external LOS detector.
Support for dual rate module (10GE/10GFC)
Standard two-wire I2C interface to external EEPROM/DOM
devices
Eliminates need for external limiting amp
Increased flexibility to accommodate design constraints.
Two reference clock inputs for 10.3 and 10.5Gb/s in a single module
Reduced module cost
I2C interface supports clock stretching by an external device
Allows I2C operation with devices which use clock stretching for flow
control
Dedicated power-up reset pin
No large capacitor required on the reset pin to the connector
Reduce number of devices on I2C bus
Two-byte I2C addressing capability to allow combined
EEPROM+DOM memory in a single device
Configurable LASI interrupt input for fast response to externally
generated alarms
Meet sub-10ms response time.
Customization of module
Configure any register on powerup from EEPROM
System Card Features
XFI compliant 10G serial interface
XFP compliant
XFP module access through MDIO
3 GPIOs, configurable as LED drivers with built-in Link and Tx/Rx
Activity modes
Eliminates additional I2C bus to control XFP module
Easily drive faceplate LEDs with no additional firmware required
Provides divide-by-64 output clock reference to XFP module
Ability to access internal registers via the I2C interface
Eliminates extra clock source on the board.
Chip can be controlled entirely from I2C interface, eliminating need for
MDIO access.
Test and Diagnostics
Multiple loopback modes
Assists in system test and diagnostics
PRBS and jitter generators and checkers
JTAG interface for Boundary Scan
AC BSCAN IEEE1149.6 on XAUI I/O
‘Extended link monitoring' feature allowing far-end link status
monitoring
Reduces need for expensive test equipment
Standard design and manufacturing test and verification
Standard design and manufacturing test and verification
Link diagnostic capability
XAUI 8B/10B decoder error counters on each lane
Ability to selectively turn-off any XAUI output
PCS scrambler/descrambler bypass mode
Register bits which mirror the state of the low-speed CMOS
inputs
Per-lane integrity checking, aids jitter tolerance testing
Full control of XAUI signal
Provides Test flexibility
Software monitoring of low-speed hardware I/O
Frequency out-of-range (sync_err) indication
Diagnosis of clock rate errors
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AppliedMicro - Confidential & Proprietary
Revision 5.11
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
