QT2022/32 - Data Sheet: DS3051
Table 3: QT2022/32 Ball Assignment & Signal Description (Continued)
Ball
Signal Name
Dir.
Type
Description
N4
TXIPMP
analog
Transmit charge pump current control
6.49kΩ resistor to GND
CMOS Inputs (note all CMOS inputs are 3.3V tolerant and all CMOS inputs with pullups are to 1.2V)
E6
TDCC
I
I
CMOS
QT2032:
Transmit data communication channel input for both section and line
SONET overhead data; clocked in using the TDCC_CLK output. Please see
Section 7.3.8, “Transport Overhead Serial Interface,” on page 48.
QT2022:
Unused. Connect to GND.
E14
LANMODE
CMOS with 50kΩ
QT2032:
pullup
LAN/WAN Mode select
0 = WAN mode enabled
1 = LAN mode enabled (default)
When LANMODE = 1, the chip will not operate in WAN mode and access to
all WIS registers is disabled. When LANMODE = 0, the chip will default to
WAN mode operation but can be set to operate in LAN mode by setting
MDIO register bit 2.7.0 to 0.
QT2022:
Unused. Leave unconnected.
C9
REFSEL622
VCXOSEL622
VCXOB
I
I
I
CMOS with 50kΩ
pulldown
QT2032:
SREFCLK frequency selection
0 = 155.52MHz (default)
1 = 622.08MHz
QT2022:
Unused. Leave unconnected.
G12
H13
CMOS with 50kΩ
pulldown
QT2032:
VCXO frequency selection
0 = 155.52MHz (default)
1 = 622.08MHz
QT2022:
Unused. Leave unconnected.
CMOS with 50kΩ
QT2032:
pullup
VCXO control loop enable pin. A low-level configures the chip to implement
a PLL using an external VCXO - see description in Section 6.2.4, “VCXO
PLL,” on page 32.
0 = enabled
1 = disabled (default)
QT2022:
Unused. Leave unconnected.
F12
VCXOONLY
I
CMOS with 50kΩ
QT2032:
pulldown
Input to indicate that the VCXO is the only reference clock available (i.e.
there is no SREFCLK input - so in non-linetiming mode, there is no
switchover to it)
0 = there is a SREFCLK input in WAN mode (default)
1 = there is no SREFCLK input in WAN mode (i.e. VCXO alone. Also set
REFSEL622 = VCXOSEL622)
QT2022:
Unused. Leave unconnected.
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