QT2022/32 - Data Sheet: DS3051
Table 3: QT2022/32 Ball Assignment & Signal Description (Continued)
Ball
Signal Name
Dir.
Type
Description
C6
PHOFF_EN
I
CMOS with 50kΩ
Phase Offset Enable pin (NEW).
pulldown
Enables adjustment of Receive CDR decision phase from nominal. Used in
conjunction with the PHASE_OFFSET pin. For test purposes only.
0 = phase offset control disabled (default)
1 = phase offset control enabled.
C2
LEGACY
I
I
CMOS with 50kΩ
pulldown
0 (default) = new register map definitions
1=reverts to 2021 register map definitions (see LEGACY mode description)
C13
RXIN_SEL
CMOS with 50kΩ
pulldown
Polarity control for RXI, 50kΩ pulldown
RXIN_SEL=0 default polarity
RXIN_SEL=1 inverted polarity
C5
TxXAUI_SEL
(SCAN_EN)
I
CMOS with 50kΩ
pulldown
XAUI Transmit path lane order control, 50kΩ pulldown
0 = default lane ordering
1 = inverted lane ordering
Enable scan in scan mode
C7
RxXAUI_SEL
I
I
CMOS with 50kΩ
pulldown
XAUI receive path lane order control, 50kΩ pulldown
0 = default lane ordering
1 = inverted lane ordering
D12
RXLOSB_I
(XFPRXLOS)
CMOS with 50kΩ
pullup to 1.2V
Receive optical signal loss indicator input (can be driven directly by
LOSOUTB or by an external source)
When XFP=0, active low indicates RX signal loss
with XFP=1, active high indicates RX signal loss
(See Section 8.2.2 on page 54)
C10
XFP
I
CMOS with 50kΩ
XFP application mode select;
pulldown
0 = non-XFP application, default; high-sensitivity input selected on 10Gb/s
input
1 = XFP application; equalization option selected on 10Gb/s input (can be
over-ridden via MDIO register bit 1.C030h.6 - ‘override_xfp_eqn’). Also
changes function of TXPLLOUT, LOSOUTB, TXFAULT, TXON,
TXENABLE, EEPROM_PROT, RXLOSB_I and TRST_N.
E8
C8
EQ_EN
I
I
CMOS with 50kΩ
pulldown
Receive Equalizer Enable pin (NEW).
Allows receive equalizer to be enabled.
0 = equalizer state determined by XFP pin (default)
1 = equalizer on.
EEPROM_PROT
(XFPMODABS)
CMOS with 50kΩ
pullup to 1.2V
With XFP=0, EEPROM interface write protection pin; Scan enable when in
scan mode
1 (default) = no writes to protected EEPROM registers allowed;
With XFP=1, high level indicates XFP module absent
F4
C4
MDC
I
I
CMOS
MDIO interface clock
TXOUT_SEL
CMOS with 50kΩ
pulldown
TXOUT polarity control, 50 kΩ pulldown
0 = default polarity
1 = inverted polarity
E3
LASI_INTB
(XFPINTB)
I
CMOS with 50kΩ
pullup to 1.2V
With XFP=0, Active low interrupt input to LASI; (See Section 8.2.12 on
page 57).
With XFP=1, active low interrupt input indicating XFP module fault
condition.
16
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