Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 2 of 7)
Ball
Signal name
Ball
Signal name
Ball
Signal name
Ball
Signal name
TRCBS0*
OV
E01
EMCTxD6
F01
G01
H01
TRCBS1*
DD
E02
E03
E04
E05
E06
GPIO19_IRQ3
EMCTxD4
IRQ4*
F02
F03
F04
F05
F06
G02
G03
G04
G05
G06
H02
H03
H04
H05
H06
EMCRxD3
EMCRxD4
TRCTS0*
EMCCD
TRCES3*
EMCMDClk
EMCRxErr
TRCES1*
EMCRxD2
GND
PerOE
EMCRxD7
IRQ7*
TRCTS2*
EMCTxD1
PerData09
TRCTS6*
EMCRefClk
IRQ8*
OV
DD
E07
E08
PerData14
PerData06
F07
F08
PerData07
PerData12
G07
G08
H07
H08
PerData00
E09
E10
E11
E12
PerAddr20
PCIX0Gnt1
PerAddr19
TESTEN
F09
F10
F11
F12
PerData08
G09
G10
G11
G12
UART0_RTS
GND
H09
H10
H11
H12
IRQ5*
UART1_DSR/CTS
PerAddr12
PerData01
PerData03
UARTSerClk
UART1_DTR/RTS
PerCS2
UART2_Tx
OV
DD
E13
E14
PerAddr0
PerAddr1
F13
F14
UART2_Rx
PerAddr9
G13
G14
H13
H14
UART0_DCD
PerAddr5
OV
DD
E15
E16
E17
E18
E19
PerAddr11
PerReady
F15
F16
F17
F18
F19
PerR/W
G15
G16
G17
G18
G19
PerErr
H15
H16
H17
H18
H19
IIC1SDA
PerAddr4
IIC0SClk
IIC1SClk
PCIE2_TX3
Reserved
Reserved
PCIE2_RX3
PCIE2_RX3
Reserved
GND
PerAddr25
PCIE1AVREG
PCIE1AV25
Reserved
PCIE2_TX3
OV
DD
E20
PCIE1_RX0
F20
PCIE2_RX2
G20
H20
PCIE2_TX1
E21
E22
E23
E24
E25
PCIE1_RX0
DQS6
F21
F22
F23
F24
F25
PCIE2_RX2
DQS6
G21
G22
G23
G24
G25
PCIE2_TX2
DM5
H21
H22
H23
H24
H25
PCIE2_TX2
MemData45
MemData42
MemData44
DQS5
MemData51
MemData49
DM6
GND
MemData43
DQS5
IRQ11*
MemData52
IRQ10*
MemData50
OV
DD
E26
F26
MemData48
G26
H26
MemData41
AMCC Proprietary
43
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
