Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 23 of 25)
Signal Name
Ball
Interface Group
Page
SYS2PLLG
SYS2PLLV
SYSClk
AD26
AE26
C16
M25
A11
SYSErr
Power
56
SysPartSel
SYSPLLG
SYSPLLV
SysReset
TCK
B14
B13
L09
System
JTAG
55
56
AA17
AB15
AD16
E12
AA13
AA14
K08
AC15
L01
TDI
TDO
TESTEN
THERMALDA
THERMALDB
TMR_CLK
TMS
Miscellaneous
57
System
JTAG
55
56
[TRCCLK] [GPIO00] High Z
[TRCBS0] [GPIO01] High Z
[TRCBS1] [GPIO02] High Z
[TRCBS2] [GPIO03] High Z
[TRCES0] [GPIO04] High Z
[TRCES1] [GPIO05] High Z
[TRCES2] [GPIO06] High Z
[TRCES3] [GPIO07] High Z
[TRCES4] [GPIO08] High Z
[TRCTS0] [GPIO09] High Z
[TRCTS1] [GPIO10] High Z
[TRCTS2] [GPIO11] High Z
[TRCTS3] [GPIO12] High Z
[TRCTS4] [GPIO13] High Z
[TRCTS5] [GPIO14] High Z
[TRCTS6] [GPIO15] High Z
TRST
H01
F01
L02
K03
G02
M05
F02
Trace
56
Note: Trace can be enabled at reset by setting
SDR0_SDSTP1[DBG] (bit 27) to 1 in the serial
bootstrap ROM.
J03
H04
J05
G05
L05
J04
K06
H06
AE17
JTAG
56
AMCC Proprietary
39
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
