Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Signal List—Ball Assignment Order
In the following table, only the primary (default) signal name is shown for each pin.
Multiplexed pins are marked with an asterisk (*). To determine the other signals that share a pin, look up the
primary signal name in Table 3 on page 17.
Table 4. Signals Listed by Ball Assignment (Sheet 1 of 7)
Ball
A01
A02
A03
A04
A05
A06
Signal name
Ball
B01
B02
B03
B04
B05
B06
Signal name
Ball
C01
C02
C03
C04
C05
C06
Signal name
EMCTxEn
Ball
D01
D02
D03
D04
D05
D06
Signal name
GND
No ball
EMCRxClk
EMCMDIO
PerData13
PerBE1
EMCTxClk
EMCTxD0
PerData11
EMCTxD5
PerData04
EMCTxErr
EMCCrS
VDD
IRQ9*
PerPar1
GND
EMCTxD3
PerAddr22
PerData02
PerPar0
PerData10
PerData15
OV
DD
A07
B07
PerAddr18
C07
PerBE0
D07
GND
A08
A09
A10
A11
A12
PerAddr17
PCIX0M66En
GND
B08
B09
B10
B11
B12
UART0_CTS
PerAddr15
EMCTxD7
ExtReset
C08
C09
C10
C11
C12
PerAddr21
PerAddr16
PerAddr14
PerCS1
D08
D09
D10
D11
D12
PerAddr23
UART0_Tx
VDD
SysPartSel
UART1_Rx
PerAddr13
UART0_Rx
UART1_Tx
UART0_DSR
OV
DD
A13
A14
B13
B14
SYSPLLV
SYSPLLG
C13
C14
UART0_DTR
UART0_RI
D13
D14
GND
GND
OV
DD
A15
A16
A17
A18
A19
PerAddr8
PerWE
B15
B16
B17
B18
B19
PerAddr2
C15
C16
C17
C18
C19
PerCS0
D15
D16
D17
D18
D19
PerAddr3
PerBLast
VDD
PerAddr10
PerAddr26
PCIE1_TX3
PCIE1_RX3
SYSCLK
PerClk
GND
PCIE1_TX3
PCIE1_RX3
PCIE1_TX2
PCIE1_RX2
PCIE1_TX2
PCIE1_RX2
OV
DD
A20
B20
PCIE1_TX1
C20
PCIE1_RX1
D20
GND
A21
A22
A23
A24
A25
PCIE1_TX1
PerAddr24
GND
B21
B22
B23
B24
B25
PCIE1_RX1
MemData63
MemData61
MemData58
DQS7
C21
C22
C23
C24
C25
PCIE1_TX0
GPIO28_IRQ12
DM7
D21
D22
D23
D24
D25
PCIE1_TX0
MemData54
VDD
MemData59
MemData62
MemData56
DQS7
MemData55
MemData53
OV
DD
A26
B26
MemData60
C26
MemData57
D26
GND
42
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
