Revision 1.26 – October 15, 2007
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
Table 20. I/O Specifications—All Speeds (Sheet 2 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
(TIS min)
(TIH min)
Ethernet RGMII Interface
GMC0RxClk
GMC0TxClk
GMC0RxD0:3
GMC0RxCtl
GMC0TxD0:3
GMC0TxCtl
n/a
5.1
5.1
5.1
5.1
5.1
n/a
5.1
5.1
5.1
5.1
5.1
n/a
n/a
6.8
6.8
6.8
6.8
6.8
n/a
6.8
6.8
6.8
6.8
6.8
n/a
1
1
n/a
n/a
0.5
0.5
n/a
n/a
3.5
3.5
GMC0RxClk
GMC0RxClk
GMC0TxClk
GMC0TxClk
1
1
n/a
n/a
n/a
n/a
GMC1RxClk
GMC1TxClk
GMC1RxD0:3
GMC1RxCtl
GMC1TxD0:3
GMC1TxCtl
1
1
n/a
n/a
0.5
0.5
n/a
n/a
3.5
3.5
GMC1RxClk
GMC1RxClk
GMC1TxClk
GMC1TxClk
1
1
n/a
n/a
n/a
n/a
GMCRefClk
Ethernet SMII Interface
SMIIRefClk
n/a
5.1
5.1
5.1
5.1
5.1
n/a
6.8
6.8
6.8
6.8
6.8
SMIISync
n/a
1.5
1.5
n/a
n/a
n/a
1
3
n/a
n/a
3
1
n/a
n/a
1
SMIIRefClk
SMIIRefClk
SMIIRefClk
SMIIRefClk
SMIIRefClk
SMII0RxD
SMII1RxD
1
SMII0TxD
n/a
n/a
SMII1TxD
3
1
Internal Peripheral Interface
IIC0SClk
27.7
27.7
27.7
27.7
27.7
27.7
15.3
n/a
12.8
12.8
12.8
12.8
12.8
12.8
10.2
n/a
IIC0SData
n/a
n/a
n/a
n/a
5
5
0
0
IIC1SClk
IIC1SData
SCPClkOut
SCPDI
5
1.5
n/a
n/a
6
SCPDO
n/a
0
UARTSerClk
UARTn_Rx
UARTn_Tx
UARTn_DCD
UARTn_DSR
UARTn_CTS
UARTn_DTR
UARTn_RI
UARTn_RTS
USB2Clk
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
19.1
n/a
8.7
n/a
n/a
n/a
n/a
n/a
19.1
n/a
8.7
n/a
19.1
19.1
USB 2.0
USB 2.0
14.6
14.6
n/a
8.7
8.7
USB2Xcvr
n/a
n/a
4
n/a
n/a
0
n/a
n/a
n/a
4
n/a
n/a
n/a
1
USB 2.0
USB 2.0
6.6
USB2Xcvr
USB2DI0:7
USB2DO0:7
USB2LS0:1
USB2OM0:1
USB2RxAct
USB2RxDV
USB2RxErr
n/a
4
n/a
0
6.6
n/a
4
n/a
1
n/a
n/a
4
n/a
0
19.1
n/a
8.7
n/a
4
n/a
1
n/a
n/a
n/a
n/a
n/a
n/a
n/a
4
1
19.1
8.7
82
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