Revision 1.26 – October 15, 2007
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
Table 19. Peripheral Interface Clock Timings (Sheet 3 of 3)
Parameter
TmrClk frequency
Min
–
Max
Units
MHz
ns
Notes
100
TmrClk period
10
–
TmrClk high time
TmrClk low time
Notes:
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock
frequency is 83 MHz.
2. An internal PLL improves this duty cycle to a worst case of 48% minimum, 52% maximum.
3. Crystals, external clocks, or external oscillators must have a maximum tolerance of ±100ppm and maximum jitter of ±100ps.Only a
frequencies of 48MHz is allowed for oscillators; only a frequencies of 48MHz is allowed for crystals. Crystals and oscillators should be
connected as shown below:
PPC440EPx
PPC440EPx
Crystal
USB2XtalOUT
C
USB2XtalIn
USB2XtalOut
USB2XtalIn
Osc
C
Crystal – Frequency: 48MHz
Resonance mode: parallel
C : 15–30pF
O
ESR: 20-60Ω
Drive level: 50–500μW
C = 2(C − C
) where
Stray
L
C is the load capacitance required by the crystal for oscillation
L
C
is the board parasitic capacitance
Stray
78
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
