Revision 1.26 – October 15, 2007
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
Table 8. Signal Functional Description (Sheet 9 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
(EOV
for Ethernet)
DD
DD
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to OV
(EOV
for Ethernet)
DD
DD
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Trace Interface
Description
I/O
Type
Notes
3.3V tolerant
2.5V CMOS
TrcBS0:2
TrcClk
Trace branch execution status.
I/O
O
Trace data capture clock, runs at 1/4 the frequency of the
processor.
3.3V tolerant
2.5V CMOS
Trace Execution Status is presented every fourth processor clock
cycle.
3.3V tolerant
2.5V CMOS
TrcES0:4
TrcTS0:6
I/O
I/O
3.3V tolerant
2.5V CMOS
Additional information on trace execution and branch status.
Power
VDD
+1.5V—Logic voltage.
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
OVDD
+3.3V—I/O (except DDR2 SDRAM and Ethernet).
+2.5V—I/O Ethernet.
EOVDD
SOVDD
+1.8V (DDR2) or +2.5V (DDR1)—I/O DDR SDRAM.
Ground for logic and I/O voltage.
GND
AVDD
+1.5V—Filtered voltage for system PLLs (analog).
Ground for system PLL voltage (analog).
AGND
EAVDD
+1.5V—Filtered voltage for Ethernet PLLs (analog).
Ground for Ethernet PLL voltage (analog).
+3.3V—Filtered voltage for USB PLL (analog).
EAGND
U1AVDD
n/a
n/a
Connect to OVDD
+3.3V—Filtered voltage for USB PHY (analog).
Connect to OVDD
.
U2AVDD
n/a
n/a
n/a
n/a
n/a
n/a
.
Ground for USB PLL (analog) voltage.
Connect to GND.
U1AGND
U2AGND
Ground for USB PHY (analog) voltage.
Connect to GND.
AMCC Proprietary
65
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
