Revision 1.26 – October 15, 2007
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
Table 12. Overshoot and Undershoot
TOS
Receiver
3.3V LVTTL
AC Overshoot (V)
DC Overshoot (V)
DC Undershoot (V)
AC Undershoot (V)
1
1
3.9
3.6
-0.16
-0.6
-0.6
0.1*TCYC
0.1*TCYC
2.5V (3.3V tolerant)
3.9
3.6
-0.16
-0.3
1.2*SOVDD
1.2*OVDD
SOVDD + 0.3
OVDD + 0.5
DDR
PCI
-0.6
0.1/MemClkOut
0.1/PCIClk
-0.2*OVDD
-0.5
Notes:
1. T
is the period of the bus clock.
CYC
1/PerClk - EBC and NAND flash interfaces.
1/GMCRXClk - GMII and MII modes
1/SMIIRefClk - SMII mode
1/GMCGRXClk - RGMII mode
1/USB2Clk - UTMI
1/TrcClk - instruction trace interface
1/IIC0Clk and 1/IIC1Clk - IIC interfaces
1/SPIClkOut - SPI
Power Sequencing
Startup sequencing of the power supply voltages is not required. However, a power-down cycle must complete
(OV and V are below +0.4V) before a new power-up cycle is started.
DD
DD
Analog Voltage Filter
The analog voltages (AVdd, EAVdd, and UnAVdd) used for the on-chip PLLs can be derived from the logic voltage, but must be
filtered before the PPC440EPx. A Separate filter, as shown below, is recommended for each voltage.
• The filter should keep the analog voltage to analog ground compression/expansion due to noise less than +50
mV.
• Keep all wire lengths as short as possible.
• Analog grounds must be brought out and connected to the digital ground plane at the filter capacitor.
• The impedance of the ferrite bead should be much greater than that of the capacitor at frequencies where
noise is expected.
VDD
AVDD, SAVDD, UnAVdd
L
L – SMT ferrite bead chip, Murata
BLM21PG600SN1
C
AGND, SAGND, UnAGND
GND
AMCC Proprietary
69
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
