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PPC440EPX-SPAFFFTS 参数 Datasheet PDF下载

PPC440EPX-SPAFFFTS图片预览
型号: PPC440EPX-SPAFFFTS
PDF下载: 下载PDF文件 查看货源
内容描述: 440EPx的PowerPC嵌入式处理器 [PowerPC 440EPx Embedded Processor]
分类和应用: PC
文件页数/大小: 94 页 / 3193 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.26 – October 15, 2007  
440EPx – PPC440EPx Embedded Processor  
Preliminary Data Sheet  
Table 8. Signal Functional Description (Sheet 5 of 9)  
Notes:  
1. Receiver input has hysteresis  
2. Must pull up (recommended value is 3kΩ to OV  
(EOV  
for Ethernet)  
DD  
DD  
3. Must pull down (recommended value is 1kΩ)  
4. If not used, must pull up (recommended value is 3kΩ to OV  
(EOV  
for Ethernet)  
DD  
DD  
5. If not used, must pull down (recommended value is 1kΩ)  
6. Strapping input during reset; pull-up or pull-down required  
Signal Name  
Description  
I/O  
Type  
Notes  
External Master Peripheral Interface  
Bus Request. Used when the PPC440EPx needs to regain  
control of peripheral interface from an external master.  
BusReq  
ExtAck  
ExtReq  
O
O
I
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
External Acknowledgement. Used by the PPC440EPx to indicate  
that a data transfer occurred.  
External Request. Used by an external master to indicate it is  
prepared to transfer data.  
1
Peripheral Reset. Used by an external master and by  
synchronous peripheral slaves.  
ExtReset  
O
3.3V LVTTL  
Note: The state of signals or clocks cannot be guaranteed until  
the ExtReset signal has been de-asserted.  
Hold Acknowledge. Used by the PPC440EPx to transfer  
ownership of peripheral bus to an external master.  
HoldAck  
HoldReq  
HoldPri  
O
I
3.3V LVTTL  
3.3V LVTTL  
Hold Request. Used by an external master to request ownership  
of the peripheral bus.  
Hold Primary. Used by an external master to indicate the priority  
of a given external master tenure.  
3.3V LVTTL  
w/pull-up  
I
Peripheral Clock. Used by an external master and by  
synchronous peripheral slaves.  
PerClk  
O
3.3V LVTTL  
1
UART Peripheral Interface  
The UART interface can be configured as follows:  
1. One 8-pin, where n = 0  
2. Two 4-pin, where n = 0 & 1  
3. One 4-pin, where n = 0 and two 2-pin, where n = 1 & 2  
4. Four 2-pin, where n = 0 & 1 & 2 & 3  
The SerClk input provides an alternative to the internally  
UARTSerClk  
UARTn_Rx  
generated serial clock. It is used in cases where the allowable  
internally generated clock rates are not satisfactory.  
I
I
3.3V LVTTL  
1, 4  
1, 4  
3.3V LVTTL  
Rcvr  
Receive data.  
UARTn_Tx  
Transmit data.  
O
I
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
UARTn_DCD  
UARTn_DSR  
UARTn_CTS  
UARTn_DTR  
UARTn_RTS  
UARTn_RI  
Data Carrier Detect.  
Data Set Ready.  
Clear To Send.  
1, 6  
1, 6  
1, 6  
1
I
I
Data Terminal Ready.  
Request To Send.  
Ring Indicator.  
O
O
I
1
1
IIC Peripheral Interface  
IIC0SClk  
IIC0 Serial Clock.  
IIC0 Serial Data.  
IIC1 Serial Clock.  
IIC1 Serial Data.  
I/O  
I/O  
I/O  
I/O  
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
1, 2  
1, 2  
1
IIC0SData  
IIC1SClk  
IIC1SData  
AMCC Proprietary  
61  
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