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PPC440EPX-SPAFFFTS 参数 Datasheet PDF下载

PPC440EPX-SPAFFFTS图片预览
型号: PPC440EPX-SPAFFFTS
PDF下载: 下载PDF文件 查看货源
内容描述: 440EPx的PowerPC嵌入式处理器 [PowerPC 440EPx Embedded Processor]
分类和应用: PC
文件页数/大小: 94 页 / 3193 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.26 – October 15, 2007  
440EPx – PPC440EPx Embedded Processor  
Preliminary Data Sheet  
Table 8. Signal Functional Description (Sheet 4 of 9)  
Notes:  
1. Receiver input has hysteresis  
2. Must pull up (recommended value is 3kΩ to OV  
(EOV  
for Ethernet)  
DD  
DD  
3. Must pull down (recommended value is 1kΩ)  
4. If not used, must pull up (recommended value is 3kΩ to OV  
(EOV  
for Ethernet)  
DD  
DD  
5. If not used, must pull down (recommended value is 1kΩ)  
6. Strapping input during reset; pull-up or pull-down required  
Signal Name  
Description  
I/O  
Type  
Notes  
External Slave Peripheral Interface  
Used by the PPC440EPx to indicate that data transfers have  
occurred.  
DMAAck0:3  
DMAReq0  
DMAReq1  
O
I
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
1
1
Used by slave peripherals to indicate they are prepared to  
transfer data.  
Used by slave peripherals to indicate they are prepared to  
transfer data.  
I
1, 5  
Used by slave peripherals to indicate they are prepared to  
transfer data.  
DMAReq2:3  
I
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
1
1
EOT0:3/TC0:3  
PerAddr02:07  
End Of Transfer/Terminal Count.  
I/O  
I/O  
Peripheral address bus used by the PPC440EPx when not in  
external master mode; otherwise, used by external master.  
1, 2  
Peripheral address bus used by the PPC440EPx when not in  
external master mode; otherwise, used by external master.  
PerAddr08:31  
PerData00:31  
I/O  
I/O  
3.3V LVTTL  
3.3V LVTTL  
Peripheral data bus used by the PPC440EPx when not in  
external master mode; otherwise, used by external master.  
Note: PerData00 is the most significant bit (msb) on this bus.  
Peripheral data bus parity used by the PPC440EPx when not in  
external master mode; otherwise, used by external master.  
PerDataPar0:3  
PerBLast  
I/O  
I/O  
3.3V LVTTL  
3.3V LVTTL  
Used by either the peripheral controller, DMA controller, or  
external master to indicates the last transfer of a memory access.  
1, 4  
PerCS0  
External peripheral device select.  
External peripheral device select.  
O
3.3V LVTTL  
3.3V LVTTL  
2
PerCS1:5  
I/O  
1, 2  
Used by either peripheral controller or DMA controller depending  
upon the type of transfer involved. When the PPC440EPx is the  
bus master, it enables the selected device to drive the bus.  
PerOE  
O
I
3.3V LVTTL  
3.3V LVTTL  
1, 2  
1
PerReady  
Used by a peripheral slave to indicate it is ready to transfer data.  
Used by the PPC440EPx when not in external master mode, as  
output by either the peripheral controller or DMA controller  
depending upon the type of transfer involved. High indicates a  
read from memory, low indicates a write to memory.  
PerR/W  
I/O  
3.3V LVTTL  
1, 2  
Otherwise, it is used by the external master as an input to  
indicate the direction of transfer.  
PerWBE0:3  
PerErr  
External peripheral data bus byte enables.  
I/O  
I
3.3V LVTTL  
3.3V LVTTL  
1, 2  
1
External Error. Used as an input to record external slave  
peripheral errors.  
60  
AMCC Proprietary  
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