Revision 1.19 – May 07, 2008
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Example 2:
In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at (2). If ECC
is enabled, Stage 3 data must be sampled (see Example 3). In this example, T and T are controlled and set by
T
TE
the software.
Figure 13. DDR SDRAM Read Cycle Timing—Example 2
DQS at pin
Data at pin
D0
D1
D3
D2
T
SIN
DQS Stage 1 C
Data in Stage 1 D
D0
D1
D3
D2
T
DIN
T
P
High
Low
D0
D1
D2
D3
Data out Stage 1
D0
D2
PLB Clock
Read Clock Delayed
T
P
D0
D1
High
D2
D3
Data out Stage 2
Low
High
Low
D2
D3
D0
D1
Data in at RDSP
without ECC
T
T
T
TE
High
Low
D0
D1
D2
D3
Data in at RDSP
with ECC
High
Low
D0
D1
D2
D3
Data out at RDSP
without ECC
(2)
T = Propagation delay from Stage 2 input to RDSP input w/o ECC
T
T
= Propagation delay from Stage 2 input to RDSP input with ECC
TE
AMCC Proprietary
83
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
