Revision 1.19 – May 07, 2008
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of
MemClkOut(0) relative to the PLB clock (T ) is provided.
MD
The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative to the
PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can be
programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the value set
in RDCT. The delay of Read Clock relative to the PLB clock (T ) shown below assumes the programmable Read
RD
Clock delay is set to zero.
Figure 10. DDR SDRAM MemClkOut0 and Read Clock Delay
PLB Clk
MemClkOut0(0)
T
MD
T
min = 600ps
MD
T
max = 1100ps
MD
Read Clock
T
RD
T
min = 300ps
max = 740ps
RD
T
RD
In operation, following the receipt of an address and read command from the PPC440GR, the SDRAM generates
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GR using a DQS
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of
Stage 1, Stage 2, or Stage 3 data for sampling at Read Sample Point flipflop (RDSP).
80
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