Revision 1.19 – May 07, 2008
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Figure 11. DDR SDRAM Read Data Path
Read Sample Point
flipflop (RDSP)
Mux
Package pins
Q
D
PLB bus
ECC
FF
Stage 3
Stage 1
Stage 2
Q
D
Q
D
D
Q
C
FF,
XL
FF
FF
Data
DQS
C
C
C
Read Select
(SDRAM0_TR1[RDSL])
(SDRAM0_TR1[RDCT])
1/4
Cycle
Delay
Programmed
Read Clock
Delay
PLB Clock
FF Timing:
T
T
T
= Input setup time = 0.2ns
= Input hold time = 0.1ns
= Propagation delay (D to Q or C to Q) = 0.4ns maximum
FF: Flip-Flop
XL: Transparent Latch
IS
IH
P
Table 26. I/O Timing—DDR SDRAM T
and T
DIN
SIN
Notes:
1. TSIN = Delay from DQS at package pin to C on Stage 1 FF.
2. TDIN = Delay from data at package pin to D on Stage 1 FF.
3. Clock speed for the values in the table is 133MHz.
4. The time values for TSIN include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).
TSIN (ns)
minimum
TSIN (ns)
maximum
TDIN (ns)
minimum
TDIN (ns)
maximum
Signal Name
Signal Name
MemData00:07
DQS0
DQS1
DQS2
DQS3
DQS8
2.74
2.75
2.74
2.76
2.77
3.70
3.69
3.69
3.69
3.68
0.86
1.87
1.86
1.86
1.85
1.83
MemData08:15
MemData16:23
MemData24:31
ECC0:7
0.87
0.89
0.88
0.89
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a
slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the eight DQS signals be matched.
AMCC Proprietary
81
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
