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PPC440GP-3RC400C 参数 Datasheet PDF下载

PPC440GP-3RC400C图片预览
型号: PPC440GP-3RC400C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 440GP嵌入式处理器 [Power PC 440GP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 83 页 / 1393 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – October 4, 2007  
440GP – Power PC 440GP Embedded Processor  
Data Sheet  
DDR SDRAM Write Operation  
The following diagram illustrates the relationship among the signals involved with a DDR write operation.  
DDR SDRAM Write Cycle Timing  
PLB Clk  
MemClkOut0  
MemClkOut0(90)  
T
SA  
Addr/Cmd  
T
DS  
T
T
SK  
DS  
T
HA  
DQS  
T
SD  
T
SD  
MemData  
T
HD  
T
HD  
T
= Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)  
= Setup time for address and command signals to MemClkOut0(90)  
SK  
T
SA  
T
T
T
T
= Hold time for address and command signals from MemClkOut0(90)  
HA  
SD  
HD  
DS  
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)  
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)  
= Delay from rising/falling edge of clock to the rising/falling edge of DQS  
72  
AMCC  
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