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PPC440GP-3RC400C 参数 Datasheet PDF下载

PPC440GP-3RC400C图片预览
型号: PPC440GP-3RC400C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 440GP嵌入式处理器 [Power PC 440GP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 83 页 / 1393 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – October 4, 2007  
440GP – Power PC 440GP Embedded Processor  
Data Sheet  
PowerPC 440 Processor Core  
The PowerPC 440 processor core is designed for high-end applications: RAID controllers, routers, switches,  
printers, set-top boxes, etc. It is the first processor core to implement the Book E PowerPC embedded architecture  
and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.  
Features include:  
• Up to 500MHz operation  
• PowerPC Book E architecture  
• 32KB I-cache, 32KB D-cache  
• Three logical regions in D-cache: locked, transient, normal  
• D-cache full line flush capability  
• 41-bit virtual address, 36-bit (64GB) physical address  
• Superscalar, out-of-order execution  
• 7-stage pipeline  
• 3 execution pipelines  
• Dynamic branch prediction  
• Memory management unit  
- 64-entry, full associative, unified TLB  
- Separate instruction and data micro-TLBs  
- Storage attributes for write-through, cache-inhibited, guarded, and big or little endian  
• Debug facilities  
- Multiple instruction and data range breakpoints  
- Data value compare  
- Single step, branch, and trap events  
- Non-invasive real-time trace interface  
• 24 DSP instructions  
- Single-cycle multiply and multiply-accumulate  
- 32 x 32 integer multiply  
- 16 x 16 -> 32-bit MAC  
Internal Buses  
The PowerPC 440GP features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-Chip  
Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores  
such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI-X bridge connect to  
the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for  
passing status and control information between the processor core and the other on-chip cores.  
Features include:  
• PLB  
- 128-bit implementation of the PLB architecture  
- Separate and simultaneous read and write data paths  
- 36-bit address  
- Simultaneous control, address, and data phases  
- Four levels of pipelining  
- Byte enable capability supporting unaligned transfers  
- 32- and 64-byte burst transfers  
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