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PPC440GP-3RC400C 参数 Datasheet PDF下载

PPC440GP-3RC400C图片预览
型号: PPC440GP-3RC400C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Power PC 440GP嵌入式处理器 [Power PC 440GP Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器PC时钟
文件页数/大小: 83 页 / 1393 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.07 – October 4, 2007  
440GP – Power PC 440GP Embedded Processor  
Data Sheet  
IIC Bus Interface  
Features include:  
• Two IIC interfaces provided  
2
• Support for Philips® Semiconductors I C Specification, dated 1995  
• Operation at 100kHz or 400kHz  
• 8-bit data  
• 10- or 7-bit address  
• Slave transmitter and receiver  
• Master transmitter and receiver  
• Multiple bus masters  
• Supports fixed V IIC interface  
DD  
• Two independent 4 x 1 byte data buffers  
• Twelve memory-mapped, fully programmable configuration registers  
• One programmable interrupt request signal  
• Provides full management of all IIC bus protocols  
• Programmable error recovery  
General Purpose Timers (GPT)  
Provides a separate time base counter and additional system timers in addition to those defined in the processor  
core.  
• 32-bit Time Base Counter driven by the OPB bus clock  
• Five 32-bit compare timers  
General Purpose IO (GPIO) Controller  
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master  
accesses.  
• 31 of the 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO  
capabilities acts as a GPIO or is used for another purpose.  
• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,  
tri-stated if output bit is 1).  
14  
AMCC  
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