Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
PPC440GP Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
DCRs
Timers
MMU
UART
IIC
PPC440
Processor Core
GP
Timers
GPIO
x2
x2
DCR Bus
45 internal
13 external
Trace
JTAG
On-chip Peripheral Bus (OPB)
Arb
32KB
I-Cache
32KB
D-Cache
DMA
OPB
Bridge
SRAM
8KB
Controller
(4-Channel)
Processor Local Bus (PLB)
External
Bus
Controller
External
Bus Master
Controller
Ethernet
x2
MAL
1 MII
or
2 RMII
66MHz max
32-bit addr
32-bit data
DDR SDRAM
Controller
PCI-X
Bridge
133MHz max
133MHz max
13-bit addr
32/64-bit data
The PPC440GP is designed using the IBM® Microelectronics Blue Logic™ methodology in which major functional
blocks are integrated together to create an application-specific product (ASIC). This approach provides a
consistent way to create complex ASICs using IBM CoreConnect Bus™ Architecture.
Note: IBM CoreConnect buses provide:
• 128-bit PLB interfaces up to 133.33MHz
• 32-bit OPB interfaces up to 66.66MHz, 266MB/s
Address Maps
The PPC440GP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various address regions which the processor can access. The
second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running
on the PPC440GP processor through the use of mtdcr and mfdcr instructions.
6
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
