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PPC440EP-3JC533C 参数 Datasheet PDF下载

PPC440EP-3JC533C图片预览
型号: PPC440EP-3JC533C
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA456, 35 X 35 MM, ROHS COMPLIANT, PLASTIC, BGA-456]
分类和应用: 时钟外围集成电路
文件页数/大小: 87 页 / 1210 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.29 – May 07, 2008  
440EP – PPC440EP Embedded Processor  
DDR1 SDRAM I/O Specifications  
Data Sheet  
The DDR1 SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from  
the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut0 is the  
same frequency as the PLB clock signal and is in phase with the PLB clock signal.  
Note: MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR  
programming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific  
application and requires a thorough understanding of the memory system in general (refer to the DDR  
SDRAM controller chapter in the PowerPC 440EP User’s Manual).  
In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted, and  
MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90°. Advancing MemClkOut0 by 90°  
creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to  
MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal.  
The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and lengths.  
Values are calculated over best case and worst case processes with speed, temperature, and voltage as follows:  
Best Case = Fast process, -40°C, +1.6V  
Worst Case = Slow process, +85°C, +1.4V  
Note: In all the following DDR tables and timing diagrams, minimum values are measured under best case  
conditions and maximum values are measured under worst case conditions.  
The signals are terminated as indicated in the figure below for the DDR timing data in the following sections.  
Figure 8. DDR SDRAM Simulation Signal Termination Model  
MemClkOut0  
10pF  
120Ω  
10pF  
MemClkOut0  
V
= SV /2  
DD  
TT  
PPC440EP  
50  
Ω
Addr/Ctrl/Data/DQS  
30pF  
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.  
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many  
factors, including the type of memory used and the board layout.  
AMCC Proprietary  
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