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PPC440EP-3JC533C 参数 Datasheet PDF下载

PPC440EP-3JC533C图片预览
型号: PPC440EP-3JC533C
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA456, 35 X 35 MM, ROHS COMPLIANT, PLASTIC, BGA-456]
分类和应用: 时钟外围集成电路
文件页数/大小: 87 页 / 1210 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.29 – May 07, 2008  
440EP – PPC440EP Embedded Processor  
Data Sheet  
Note: The timing data in the following tables is based on simulation runs using Einstimer.  
Table 22. I/O Timing—DDR SDRAM T  
DS  
Notes:  
1. All of the DQS signals are referenced to MemClkOut0(0).  
2. Clock speed is 133MHz.  
3. The TDS values in the table include 3/4 of a cycle at 133MHz (7.5ns x 0.75 = 5.625 ns).  
4. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle  
time for the lower clock frequency (TDS - 5.625 + 0.75TCYC).  
TDS (ns)  
Signal Name  
Minimum  
5.76  
Maximum  
5.86  
DQS0  
DQS1  
DQS2  
DQS3  
DQS8  
5.78  
5.91  
5.82  
5.90  
5.79  
5.89  
5.75  
5.88  
Table 23. I/O Timing—DDR SDRAM T , T , and T  
SK SA  
HA  
Notes:  
1. Clock speed is 133MHz. TSK is referenced to MemClkOut0(0). TSA and THA are referenced to MemClkOut0(90).  
2. To obtain adjusted TSA values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and subtract  
TSK maximum (0.75TCYC - TSKmax).  
3. To obtain adjusted THA values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add  
TSK minimum (0.25TCYC + TSKmin).  
TSK (ns)  
TSA (ns)  
THA (ns)  
Signal Name  
Minimum  
0.11  
Maximum  
0.32  
Minimum  
5.31  
Minimum  
1.99  
MemAddr00:12  
BA0:1  
0.07  
0.31  
5.32  
1.95  
BankSel0:3  
ClkEn0:3  
CAS  
0.05  
0.25  
5.38  
1.93  
0.07  
0.28  
5.35  
1.95  
0.05  
0.31  
5.32  
1.93  
RAS  
0.05  
0.28  
5.35  
1.93  
WE  
0.08  
0.22  
5.41  
1.96  
Table 24. I/O Timing—DDR SDRAM T and T  
SD  
HD  
Notes:  
1. TSD and THD are measured under worst case conditions.  
2. Clock speed for the values in the table is 133MHz.  
3. The time values in the table include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).  
4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.875 ns from the values in the table and add  
1/4 of the cycle time for the lower clock frequency (e.g., TSD - 1.875 + 0.25TCYC).  
TSD (ns)  
THD (ns)  
Signal Names  
MemData00:07, DM0  
MemData08:15, DM1  
MemData16:23, DM2  
MemData24:31, DM3  
ECC0:7, DM8  
Reference Signal  
DQS0  
1.795  
1.775  
1.745  
1.765  
1.685  
1.866  
1.865  
1.862  
1.864  
1.857  
DQS1  
DQS2  
DQS3  
DQS8  
78  
AMCC Proprietary  
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