欢迎访问ic37.com |
会员登录 免费注册
发布采购

PPC440EP-3JC533C 参数 Datasheet PDF下载

PPC440EP-3JC533C图片预览
型号: PPC440EP-3JC533C
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA456, 35 X 35 MM, ROHS COMPLIANT, PLASTIC, BGA-456]
分类和应用: 时钟外围集成电路
文件页数/大小: 87 页 / 1210 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号PPC440EP-3JC533C的Datasheet PDF文件第58页浏览型号PPC440EP-3JC533C的Datasheet PDF文件第59页浏览型号PPC440EP-3JC533C的Datasheet PDF文件第60页浏览型号PPC440EP-3JC533C的Datasheet PDF文件第61页浏览型号PPC440EP-3JC533C的Datasheet PDF文件第63页浏览型号PPC440EP-3JC533C的Datasheet PDF文件第64页浏览型号PPC440EP-3JC533C的Datasheet PDF文件第65页浏览型号PPC440EP-3JC533C的Datasheet PDF文件第66页  
Revision 1.29 – May 07, 2008  
440EP – PPC440EP Embedded Processor  
Data Sheet  
Table 10. Recommended DC Operating Conditions (Sheet 2 of 2)  
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended  
conditions can affect device reliability.  
Parameter  
Input Logic Low (2.5V SSTL)  
Symbol  
Minimum  
Typical  
Maximum  
Unit  
V
Notes  
SVREF-0.18  
-0.3  
Input Logic Low (2.5V CMOS, 3.3V tolerant receiver)  
Input Logic Low (3.3V PCI)  
0.7  
V
VIL  
0.35OVDD  
-0.5  
0
V
1
Input Logic Low (3.3V LVTTL)  
+0.8  
V
SVDD  
Output Logic High (2.5V SSTL)  
+1.95  
2.0  
V
SVDD  
OVDD  
OVDD  
Output Logic High (2.5V CMOS, 3.3V tolerant receiver)  
Output Logic High (3.3V PCI)  
V
VOH  
0.9OVDD  
V
1
1
Output Logic High (3.3V LVTTL)  
+2.4  
0
V
V
V
V
V
Output Logic Low (2.5V SSTL)  
0.55  
0.4  
Output Logic Low (2.5V CMOS, 3.3V tolerant receiver)  
Output Logic Low (3.3V PCI)  
VOL  
0.1OVDD  
Output Logic Low (3.3V LVTTL)  
0
0
+0.4  
0
IIL1  
IIL2  
Input Leakage Current (No pull-up or pull-down)  
μA  
μA  
μA  
V
Input Leakage Current for Pull-Down  
0 (LPDL)  
-150 (LPDL)  
200 (MPUL)  
0 (MPUL)  
+3.9  
IIL3  
Input Leakage Current for Pull-Up  
VIMAO  
VIMAU  
VOMAO  
VOMAU3  
Input Max Allowable Overshoot (3.3V LVTTL)  
Input Max Allowable Undershoot (3.3V LVTTL)  
Output Max Allowable Overshoot (3.3V LVTTL)  
Output Max Allowable Undershoot (3.3V LVTTL)  
4, 5  
4, 5  
4, 5  
4, 5  
-0.6  
-0.6  
V
+3.9  
V
V
Case Temperature:  
333MHz and 400MHz parts in any package  
-40  
-40  
-40  
-40  
-90  
-100  
+85  
+95  
533MHz parts in any package  
667MHz parts in the E-PBGA package  
667MHz parts in the TE-PBGA package.  
TC  
°C  
Notes:  
1. PCI drivers meet PCI specifications.  
2. SVREF = SVDD/2  
3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the  
PPC440EP. See “Absolute Maximum Ratings” on page 61.  
4. Overshoot and undershoot voltages are for 10% duty cycle.  
5. The time for overshoot or undershoot is time above OVDD and the time below 0V.  
62  
AMCC Proprietary  
 复制成功!