Revision 1.29 – May 07, 2008
440EP – PPC440EP Embedded Processor
Data Sheet
Table 8. Signal Functional Description (Sheet 8 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
System Interface
Description
I/O
Type
Notes
3.3V tolerant
2.5V CMOS
SysClk
SysErr
Main system clock input.
Clock
O
3.3V tolerant
2.5V CMOS
Set to 1 when a machine check is generated.
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to initiate a system reset. A system
reset can also be initiated by software. Implemented as an open-
drain output (two states; 0 or open circuit).
3.3V tolerant
2.5V CMOS
SysReset
I/O
1, 2
1, 2
Halt
Halt from external debugger.
I
I
3.3V LVTTL
3.3V tolerant
2.5V CMOS
TmrClk
Processor timer external input clock.
General purpose I/O 0 through 63. To access these functions,
software must set DCR register bits.
GPIO00:63
TestEn
I/O
Multiplex
3.3V LVTTL
Multiplex
Test Enable.
I
I
3
Receiver Inhibit. Active only when TestEn is active. Used for
manufacturing test only.
RcvrInh
Mode Control. Active only when TestEn is active. Used for
manufacturing test only.
ModeCtrl
LeakTest
RefEn
I
I
Multiplex
Multiplex
Multiplex
Leakage Test. Active only when TestEn is active. Used for
manufacturing test only.
Reference Enable. Active only when TestEn is active. Used for
manufacturing test only.
I
Driver Inhibit. Active only when TestEn is active. Used for
manufacturing test only.
3.3V tolerant
2.5V CMOS
DrvrInh1
DrvrInh2
PSROOut
I
Driver Inhibit. Active only when TestEn is active. Used for
manufacturing test only.
I
3.3V LVTTL
Module characterization and screening. Use for test purposes only.
Tie down as specified in Note 3 for normal operation.
Perf screen
ring osc
O
1, 3
AMCC Proprietary
59