Revision 1.29 – May 07, 2008
440EP – PPC440EP Embedded Processor
Data Sheet
Table 8. Signal Functional Description (Sheet 4 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
External Slave Peripheral Interface
Used by the PPC440EP to indicate that data transfers have
occurred.
DMAAck0:3
O
Multiplex
Used by slave peripherals to indicate they are prepared to transfer
data.
DMAReq0:3
I
Multiplex
Multiplex
1
1
EOT0:3/TC0:3
PerAddr02:07
End Of Transfer/Terminal Count.
I/O
I/O
Peripheral address bus used by PPC440EP when not in external
master mode, otherwise used by external master.
3.3V LVTTL
1, 2
Peripheral address bus used by PPC440EP when not in external
master mode, otherwise used by external master.
PerAddr08:31
I/O
3.3V LVTTL
Used by either the peripheral controller, DMA controller, or
external master to indicate the last transfer of a memory access.
PerBLast
PerCS0:5
I/O
O
3.3V LVTTL
3.3V LVTTL
1, 4
2
External peripheral device select.
Peripheral data bus used by PPC440EP when not in external
master mode, otherwise used by external master.
PerData00:15
I/O
3.3V LVTTL
1
2
Note: PerData00 is the most significant bit (msb) on this bus.
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC440EP is the bus
master, it enables the selected device to drive the bus.
PerOE
O
I
3.3V LVTTL
3.3V LVTTL
PerReady
Used by a peripheral slave to indicate it is ready to transfer data.
Used by the PPC440EP when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a read
from memory, low indicates a write to memory.
PerR/W
I/O
3.3V LVTTL
1, 2
Otherwise, it used by the external master as an input to indicate
the direction of transfer.
PerWBE0:1
PerErr
External peripheral data bus byte enables.
I/O
I/O
3.3V LVTTL
3.3V LVTTL
1, 2
1
External Error. Used as an input to record external slave peripheral
errors.
AMCC Proprietary
55
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
