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PPC440EP-3JC533C 参数 Datasheet PDF下载

PPC440EP-3JC533C图片预览
型号: PPC440EP-3JC533C
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA456, 35 X 35 MM, ROHS COMPLIANT, PLASTIC, BGA-456]
分类和应用: 时钟外围集成电路
文件页数/大小: 87 页 / 1210 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.29 – May 07, 2008  
440EP – PPC440EP Embedded Processor  
Data Sheet  
Table 8. Signal Functional Description (Sheet 2 of 9)  
Notes:  
1. Receiver input has hysteresis  
2. Must pull up (recommended value is 3kΩ to 3.3V)  
3. Must pull down (recommended value is 1kΩ)  
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)  
5. If not used, must pull down (recommended value is 1kΩ)  
6. Strapping input during reset; pull-up or pull-down required  
Signal Name  
DDR SDRAM Interface  
BA0:1  
Description  
I/O  
Type  
Notes  
Bank Address supporting up to four internal banks.  
Selects up to four external DDR SDRAM banks.  
Column Address Strobe.  
O
O
O
O
2.5V SSTL_2  
2.5V SSTL_2  
2.5V SSTL_2  
2.5V SSTL_2  
BankSel0:3  
CAS  
ClkEn  
Clock Enable.  
DM0:3  
DM8  
Memory write data byte lane masks. DM8 is the byte lane mask for  
the ECC byte lane.  
O
2.5V SSTL_2  
2.5V SSTL_2  
DQS0:3  
DQS8  
Byte lane data strobe. DQS8 is the data strobe for the ECC byte  
lane.  
I/O  
ECC0:7  
ECC check bits 0:7.  
Memory address bus.  
I/O  
O
2.5V SSTL_2  
2.5V SSTL_2  
MemAddr00:12  
MemClkOut0  
MemClkOut0  
2.5V SSTL_2  
Diff driver  
Subsystem clock.  
Memory data bus.  
Self refresh.  
O
I/O  
I
MemData00:31  
MemSelfRef  
2.5V SSTL_2  
3.3V tolerant  
2.5V CMOS  
5
RAS  
Row Address Strobe.  
Write Enable.  
O
O
I
2.5V SSTL_2  
2.5V SSTL_2  
Volt ref receiver  
WE  
SVREF1  
SSTL reference voltage.  
Volt ref pin  
(supplemental)  
SVREF2A:B  
Supplemental SSTL reference voltage.  
I
AMCC Proprietary  
53  
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