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PPC440EP-3JC533C 参数 Datasheet PDF下载

PPC440EP-3JC533C图片预览
型号: PPC440EP-3JC533C
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA456, 35 X 35 MM, ROHS COMPLIANT, PLASTIC, BGA-456]
分类和应用: 时钟外围集成电路
文件页数/大小: 87 页 / 1210 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.29 – May 07, 2008  
440EP – PPC440EP Embedded Processor  
Data Sheet  
Table 8. Signal Functional Description (Sheet 1 of 9)  
Notes:  
1. Receiver input has hysteresis  
2. Must pull up (recommended value is 3kΩ to 3.3V)  
3. Must pull down (recommended value is 1kΩ)  
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)  
5. If not used, must pull down (recommended value is 1kΩ)  
6. Strapping input during reset; pull-up or pull-down required  
Signal Name  
PCI Interface  
Description  
I/O  
Type  
Notes  
PCIAD00:31  
PCIC0:3/BE0:3  
PCIClk  
Address/Data bus (bidirectional).  
I/O  
I/O  
I
3.3V PCI  
3.3V PCI  
3.3V PCI  
PCI Command/Byte Enables.  
Provides timing to the PCI interface for PCI transactions.  
5
Indicates the driving device has decoded its address as the target  
of the current access.  
PCIDevSel  
PCIFrame  
I/O  
I/O  
3.3V PCI  
3.3V PCI  
(PCI 2.2 specification requires 8.2kΩ pull up on host system)  
Driven by the current master to indicate beginning and duration of  
an access.  
(PCI 2.2 specification requires 8.2kΩ pull up on host system)  
Indicates that the specified agent is granted access to the bus.  
When the internal arbiter is enabled, output is PCIGnt0. When the  
internal arbiter is disabled, output is Req.  
PCIGnt0/Req  
PCIGnt1:5  
O
O
3.3V PCI  
3.3V PCI  
Indicates that the specified agent is granted access to the bus.  
Used only when internal PCI arbiter enabled.  
Used as a chip select during configuration read and write  
transactions.  
PCIIDSel  
PCIINT  
I
3.3V PCI  
3.3V PCI  
Level sensitive PCI interrupt.  
O
Indicates initiating agent’s ability to complete the current data  
phase of the transaction.  
PCIIRDY  
PCIPar  
I/O  
I/O  
I/O  
3.3V PCI  
3.3V PCI  
3.3V PCI  
(PCI 2.2 specification requires 8.2kΩ pull up on host system)  
Even parity.  
Reports data parity errors during all PCI transactions except a  
Special Cycle.  
PCIPErr  
(PCI 2.2 specification requires 8.2kΩ pull up on host system)  
Indicates to the PCI arbiter that the specified agent wishes to use  
the bus. When the internal arbiter is enabled, input is PCIReq0.  
When internal arbiter is disabled, input is Gnt.  
PCIReq0/Gnt  
I
3.3V PCI  
4
4
An indication to the PCI arbiter that the specified agent wishes to  
use the bus. Used only when internal PCI arbiter enabled.  
PCIReq1:5  
PCIReset  
I
3.3V PCI  
3.3V PCI  
Brings PCI device registers and logic to a consistent state.  
O
Reports address parity errors, data parity errors on the Special  
Cycle command, or other catastrophic system errors.  
PCISErr  
PCIStop  
PCITRDY  
I/O  
I/O  
I/O  
3.3V PCI  
3.3V PCI  
3.3V PCI  
(PCI 2.2 specification requires 8.2kΩ pull up on host system)  
Current target is requesting the master to stop the current  
transaction.  
(PCI 2.2 specification requires 8.2kΩ pull up on host system)  
Target agent’s ability to complete the current data phase of the  
transaction.  
(PCI 2.2 specification requires 8.2kΩ pull up on host system)  
52  
AMCC Proprietary  
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