Revision 1.26 – April 25, 2007
440EP – PPC440EP Embedded Processor
Data Sheet
Table 16. I/O Specifications—All Speeds (Sheet 1 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
async
async
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
(TIS min)
(TIH min)
PCI Interface
PCIAD31:00
PCIC3:0/BE3:0
PCIClk
5
5
0
0
6
6
2
2
0.5
0.5
na
1.5
1.5
na
PCIClk
PCIClk
dc
5
dc
0
PCIDevSel
PCIFrame
PCIGnt0:5
PCIIDSel
6
6
2
2
0.5
0.5
0.5
na
1.5
1.5
1.5
na
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
5
0
n/a
5
n/a
0
6
2
n/a
6
n/a
2
PCIINT
n/a
5
n/a
0
0.5
0.5
0.5
0.5
na
1.5
1.5
1.5
1.5
na
PCIIRDY
6
2
PCIPar
5
0
6
2
PCIPErr
5
0
6
2
PCIReq0:5
PCIReset
PCISErr
5
0
n/a
n/a
6
n/a
n/a
2
n/a
5
n/a
0
na
na
0.5
0.5
0.5
1.5
1.5
1.5
PCIStop
5
0
6
2
PCITRDY
Ethernet MII Interface
EMCCD
5
0
6
2
10
10
10
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
na
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
na
1, async
1, async
EMCCrS
EMCDV
EMCMDClk
EMCMDIO
EMCRxClk
EMCRxD0:3
EMCRxErr
EMCTxClk
EMCTxD0:3
EMCTxEn
EMCTxErr
1, async
10
n/a
10
10
n/a
10
20
n/a
n/a
n/a
n/a
20
0
n/a
n/a
n/a
n/a
0
EMCMDClk
1
1, async
EMCRxClk
EMCRxClk
1
10
10
1
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1, async
5.1
5.1
5.1
6.8
6.8
6.8
EMCTxClk
EMCTxClk
EMCTxClk
1
1
1
20
0
20
0
for MII,
RMII,
SMII
RejectPkt
0481
0.277
EMCRxClk
Ethernet RMII Interface
EMC0CRSDV
EMC0RxD0:1
EMC0RxErr
4
4
2
2
n/a
n/a
n/a
n/a
n/a
0
5.1
5.1
5.1
6.8
6.8
6.8
EMCRefClk
EMCRefClk
EMCRefClk
1
1
1
4
2
n/a
EMC0TxD0:1
EMC1CRSDV
EMC1RxD0:1
EMC1RxErr
n/a
4
n/a
2
12.5
n/a
n/a
n/a
n/a
0
4
2
n/a
5.1
5.1
5.1
5.1
6.8
6.8
6.8
6.8
EMCRefClk
EMCRefClk
EMCRefClk
1
4
2
n/a
1
1
EMC1TxD0:1
EMCRefClk
n/a
n/a
n/a
n/a
12.5
n/a
n/a
1, async
AMCC Proprietary
67
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
