Revision 1.26 – April 25, 2007
440EP – PPC440EP Embedded Processor
Data Sheet
Table 17. I/O Specifications—333MHz to 533MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
(TIS min)
(TIH min)
External Slave Peripheral Interface
DMAAck0:1
DMAAck2:3
DMAReq0:3
EOT0:1/TC0:1
EOT2:3/TC2:3
PerAddr02:31
PerBLast
n/a
n/a
11.7
11.7
11.7
4
n/a
n/a
0.5
0.5
0.5
1
10
10
1
5.1
15.3
na
6.8
10.2
na
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
1
n/a
10
n/a
1
5.1
6.8
10
1
15.3
15.3
15.3
10.3
15.3
15.3
15.3
15.3
15.3
10.2
10.2
10.2
7.1
7.2
6.5
6.5
7.2
6.5
n/a
6.5
6.5
1.5
1.5
1.5
1.5
1.5
n/a
1.5
1.5
4
1
PerCS0:5
n/a
4
n/a
1
PerData00:15
PerOE
10.2
10.2
10.2
10.2
10.2
n/a
6
n/a
1
PerReady
PerR/W
4
1
PerWBE0:1
4
1
External Master Peripheral Interface
BusReq
n/a
n/a
4
n/a
n/a
1
6.5
6.5
n/a
6.0
6.5
n/a
n/a
n/a
n/a
1.5
1.5
n/a
1.5
1.5
n/a
n/a
n/a
n/a
7.1
7.1
9.6
9.6
n/a
10.2
9.6
na
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
ExtAck
ExtReq
n/a
ExtReset
HoldAck
HoldReq
HoldPri
n/a
n/a
4
n/a
n/a
1
15.3
7.1
na
4
1
na
na
PerClk
n/a
6
n/a
1
15.3
10.3
10.2
7.1
PLB Clk
PerClk
1
PerErr
NAND Flash Interface
NFALE
n/a
n/a
n/a
4
n/a
n/a
n/a
1
6.5
6.5
6.5
n/a
6.5
6.5
1.5
1.5
1.5
n/a
1.5
1.5
5.1
10.3
5.1
na
6.8
7.1
6.8
na
NFCE0:3
NFCLE
NFRdyBusy
NFREn
n/a
n/a
n/a
n/a
5.1
5.1
6.8
6.8
NFWEn
70
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
