Revision 1.26 – April 25, 2007
440EP – PPC440EP Embedded Processor
I/O Specifications
Data Sheet
Table 15. Peripheral Interface Clock Timings
Parameter
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
PCIClk input high time
Min
Max
Units
MHz
ns
Notes
–
66.66
15
–
40% of nominal period
60% of nominal period
ns
PCIClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
MHz
ns
400
–
EMCMDClk output high time
EMCMDClk output low time
EMCTxClk input frequency MII(RMII)
EMCTxClk period MII(RMII)
EMCTxClk input high time
160
160
–
ns
–
ns
2.5(5)
25(50)
MHz
ns
40(20)
400(200)
35% of nominal period
35% of nominal period
2.5(5)
–
ns
EMCTxClk input low time
–
ns
EMCRxClk input frequency MII(RMII)
EMCRxClk period MII(RMII)
EMCRxClk input high time
25(50)
MHz
ns
40(20)
400(200)
35% of nominal period
35% of nominal period
–
–
ns
EMCRxClk input low time
ns
PerClk (and OPB clock) output frequency (for ext. master or
sync. slaves)
–
66.66
MHz
PerClk period
15
–
ns
ns
ns
PerClk output high time
PerClk output low time
50% of nominal period
33% of nominal period
66% of nominal period
50% of nominal period
1000/(2TOPB1+2ns)
UARTSerClk input frequency
UARTSerClk period
–
MHz
ns
1
1
1
1
2TOPB+2
TOPB+1
–
–
UARTSerClk input high time
ns
T
OPB+1
UARTSerClk input low time
USB2Clk input frequency
USB1Clk input frequency
–
ns
60
48
60
48
MHz
MHz
AMCC Proprietary
65
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
