Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 6. Signal Functional Description (Sheet 5 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Description
I/O
Type
Notes
5V tolerant
3.3V LVTTL
TDO
Test data out.
O
JTAG test clock. The frequency of this input can range from DC to
25MHz.
5V tolerant
3.3V LVTTL
TCK
I
I
1, 4
5
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller.
5V tolerant
3.3V LVTTL
TRST
System Interface
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
(two states; 0 or open circuit).
5V tolerant
3.3V LVTTL
SysReset
I/O
1, 2
5V tolerant
3.3V LVTTL
SysErr
Halt
Set to 1 when a Machine Check is generated.
Halt from external debugger.
O
I
6
1, 2
1
5V tolerant
3.3V LVTTL
General Purpose I/O. All of the GPIO signals are multiplexed with
other signals.
5V tolerant
3.3V LVTTL
GPIO00:31
I/O
Test Enable. Used only for manufacturing tests. Pull down for normal
operation.
1.8V CMOS
w/pull-down
TestEn
SysClk
I
I
I
Main system clock input.
3.3V LVTTL
5V tolerant
3.3V LVTTL
[RejectPkt0:1]
External request to reject a packet.
AVDD
AGND
Clean voltage input for the PLL.
Clean Ground input for the PLL.
I
I
Trace Interface
[TS1E]
[TS2E]
Even Trace execution status. To access this function, software must
toggle a DCR bit
5V tolerant
3.3V LVTTL
O
O
O
O
1
1
1
1
[TS1O]
[TS2O]
Odd Trace execution status. To access this function, software must
toggle a DCR bit
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
[TS3:6]
Trace status. To access this function, software must toggle a DCR bit
Trace interface clock. Operates at half the CPU core frequency. To
access this function, software must toggle a DCR bit
5V tolerant
3.3V LVTTL
[TrcClk]
Power
Ground
GND
na
na
na
na
na
na
Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also
thermal balls.
OVDD
Output driver voltage—3.3V.
AMCC
35
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
