Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 6. Signal Functional Description (Sheet 1 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Description
I/O
Type
Notes
PCI Interface
PCI Address/Data Bus. Multiplexed address and data bus.
Note: The target device number is driven on PCIAD11:31 for PCI
Type 0 configuration transactions.
Connect the target IDSEL associated with device:
1 to PCIAD16
5V tolerant
3.3V PCI
PCIAD00:31
I/O
2 to PCIAD17
...
21 to PCIAD31.
5V tolerant
3.3V PCI
PCIC3:0/BE3:0
PCIClk
PCI bus command and byte enables.
I/O
I
5V tolerant
3.3V PCI
PCIClk is used as the asynchronous PCI clock when in asynch mode.
PCIFrame is driven by the current PCI bus master to indicate the
beginning and duration of a PCI access.
5V tolerant
3.3V PCI
PCIFrame
I/O
2
PCI parity. Parity is even across PCIAD00:31 and PCIC3:0/BE3:0.
PCIParity is valid one cycle after either an address or data phase.
The PCI device that drove PCIAD00:31 is responsible for driving
PCIParity on the next PCI bus clock.
5V tolerant
3.3V PCI
PCIParity
I/O
PCIIRDY is driven by the current PCI bus master. Assertion of
PCIIRDY indicates that the PCI initiator is ready to transfer data.
5V tolerant
3.3V PCI
PCIIRDY
PCITRDY
I/O
I/O
2
2
The target of the current PCI transaction drives PCITRDY. Assertion
of PCITRDY indicates that the PCI target is ready to transfer data.
5V tolerant
3.3V PCI
The target of the current PCI transaction can assert PCIStop to
indicate to the requesting PCI master that it wants to end the current
transaction.
5V tolerant
3.3V PCI
PCIStop
I/O
2
2
PCIDevSel is driven by the target of the current PCI transaction. A
PCI target asserts PCIDevSel when it has decoded an address and
command encoding and claims the transaction.
5V tolerant
3.3V PCI
PCIDevSel
PCIIDSel
I/O
I
PCIIDSel is used during configuration cycles to select the PCI slave
interface for configuration.
5V tolerant
3.3V PCI
PCI interrupt. Open-drain output (two states; 0 or open circuit)
or
5V tolerant
3.3V PCI
PCIINT
O
Peripheral write enable. Low when any of the four PerWBE0:3 write
byte enables are low.
PCISErr is used for reporting address parity errors or catastrophic
failures detected by a PCI target.
5V tolerant
3.3V PCI
PCISErr
PCIPErr
I/O
I/O
2
2
PCIPErr is used for reporting data parity errors on PCI transactions.
PCIPErr is driven active by the device receiving PCIAD00:31,
PCIC3:0/BE3:0, and PCIParity, two PCI clocks following the data in
which bad parity is detected.
5V tolerant
3.3V PCI
5V tolerant
3.3V PCI
PCIReset
PCI specific reset.
O
I
Multipurpose signal, used as PCIReq0 when internal arbiter is used,
and as Gnt when external arbiter is used.
5V tolerant
3.3V PCI
PCIReq0/Gnt
AMCC
31
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
