Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 6. Signal Functional Description (Sheet 6 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Description
I/O
Type
Notes
VDD
Logic voltage—1.8V.
na
na
na
Other pins
Reserved pins. Do not make voltage, ground, or signal connections to
these pins.
Reserved
na
na
na
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic
Supply Voltage (Internal Logic)
Symbol
Value
Unit
V
VDD
0 to +1.95
0 to +3.6
OVDD
AVDD
VIN
Supply Voltage (I/O Interface)
V
PLL Supply Voltage
0 to +1.95
0 to +1.95
0 to +3.6
V
Input Voltage (1.8V CMOS receivers)
Input Voltage (3.3V LVTTL receivers)
Input Voltage (5.0V LVTTL receivers)
Storage Temperature Range
V
VIN
V
VIN
0 to +5.5
V
TSTG
TC
-55 to +150
-40 to +120
°C
°C
Case temperature under bias
Note: All specified voltages are with respect to GND.
Table 8. Package Thermal Specifications
The PPC405EP is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the E-
PBGA packages in a convection environment are as follows:
Airflow
ft/min (m/sec)
Package—Thermal Resistance
Symbol
Unit
0 (0)
100 (0.51)
200 (1.02)
31mm, 385-balls—Junction-to-Case
θJC
θCA
2
2
2
°C/W
°C/W
31mm, 385-balls—Case-to-Ambient1
17.8
16.8
16.1
Note:
1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.
b. TA = TC – P×θCA, where TA is ambient temperature and P is power consumption.
36
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
