Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 15. I/O Specifications—Group 2
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405EP package pin. System designers must use the PPC405EP IBIS
model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that
the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. IOH is specified at 2.4V and IOL is specified at 0.4V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
IOH
(minimum)
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
IOL
(minimum)
(TIS min)
(TIH min)
SDRAM Interface
BA1:0
na
na
na
na
na
na
1.6
na
na
na
na
na
na
na
na
1
4.7
4.5
4.8
4.1
4.7
4.8
4
2
15.3
15.3
15.3
28.7
15.3
15.3
15.3
15.3
15.3
10.2
10.2
10.2
19.3
10.2
10.2
10.2
10.2
10.2
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BankSel3:0
CAS
1.7
2
ClkEn0:1
DQM0:3
1.6
1.9
2.1
1.2
2.1
2
MemAddr12:00
MemData00:31
RAS
na
na
5
WE
4.9
External Slave Peripheral Interface
PerAddr06:31
[PerBLast]
na
4
na
1
3.8
8
1.6
0
15.3
12
10.2
8
PerClk
PerClk
PerCS0
[PerCS1:4]
na
na
4.1
1.5
10.3
7.1
PerClk
PerData00:31
PerOE
5
1
6.4
4.1
4.1
na
1.5
1.5
1.6
na
15.3
10.3
10.3
na
10.2
7.1
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
na
na
6.5
na
na
na
na
na
1
PerR/W
7.1
PerReady
PerWBE0:3
ExtReset
PerClk
na
na
na
na
4.1
na
1.6
na
10.3
15.3
15.3
7.1
10.2
10.2
0.4
-0.2
4
AMCC
47
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
