Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
Data Sheet
Table 13. Peripheral Interface Clock Timings
Parameter
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
Min
Note 1
15
Max
Units
MHz
ns
66.66
Note 1
PCIClk input high time
40% of nominal period
60% of nominal period
ns
PCIClk input low time
40% of nominal period
60% of nominal period
ns
EMC0MDClk output frequency
EMC0MDClk period
–
2.5
MHz
ns
400
–
EMC0MDClk output high time
EMC0MDClk output low time
PHY0Tx0:1Clk input frequency
PHY0Tx0:1Clk period
160
–
ns
160
–
ns
2.5
25
MHz
ns
40
400
PHY0Tx0:1Clk input high time
PHY0Tx0:1Clk input low time
PHY0Rx0:1Clk input frequency
PHY0Rx0:1Clk period
35% of nominal period
–
ns
35% of nominal period
–
ns
2.5
25
MHz
ns
40
400
PHY0Rx0:1Clk input high time
PHY0Rx0:1Clk input low time
PerClk output frequency
PerClk period
35% of nominal period
35% of nominal period
–
–
ns
–
ns
66.66
MHz
ns
15
–
PerClk output high time
45% of nominal period
45% of nominal period
55% of nominal period
55% of nominal period
± 0.3
ns
PerClk output low time
ns
PerClk clock edge stability (phase jitter, cycle to cycle)
Note:
ns
1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405EP Embedded Processor
User’s Manual for more information.
AMCC
43
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
