Revision 1.09 - August 21, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 7. DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut
T
SA
Addr/Cmd
T
T
SK
DS
T
HA
T
DS
DQS
T
SD
T
SD
MemData
T
HD
T
HD
T
T
= Delay from rising edge of MemClkOut to rising/falling edge of signal (skew)
= Setup time for address and command signals to MemClkOut
SK
SA
T
T
T
= Hold time for address and command signals from MemClkOut
HA
SD
HD
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
T
DS
Note: The timing data in the following tables is based on simulation runs using Einstimer.
Table 21. I/O Timing—DDR SDRAM T
DS
Notes:
1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle.
2. Clock speed is 200MHz.
TDS (ns)
Signal Name
Minimum
Maximum
DQS0
DQS1
DQS2
DQS3
DQS4
4
4
4
4
4
6
6
6
6
6
60
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