Revision 1.09 - August 21, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Figure 8. DDR SDRAM Read Data Path
FF: Flip-Flop
DDR 1X Clock
Ext FeedBack
Signals
Driver
MemDCFdbkD
FeedBack
Signal Gen
Coarse Delay
Read Start
CAS Lat Delay
DDR 1X Clock
Read Latency adjust circuit
Rec
Stage 2 Store
Oversampling
Fine Delay
Fine Delay
MemDCFdbkR
DQS aligned
FBK signal
Cycles
Delay
+1
Feedback
Data Capture
Window
T1 T2 T3 T4
adjust
Oversampling
Clock
0
1
Q2_Ovs
7
Package
pins
Mux
0
2
4
6
FF
FF
Compare
FF
Q2
PLB bus
Read FIFO
[0:63]
D
(x32)
C
Mux
Upper
DQS Rising
Edge Sync
DQ
Data
(x32)
Stage 2
Stage 3
Stage 1
Lower
FF
FF
FF
1
3
5
Q3
PLB bus
FF
D
[64:127]
(x32)
7
C
Programmed
Read DQS
Delay
DQS Falling
Edge Sync
DQS
DDR 1X Clock
PLB 1X Clock
DDR SDRAM Read Cycle Timing
The following diagram illustrates the relationship of the signals involved with a DDR read operation.
Figure 9. DDR SDRAM Memory Data and DQS
DQS
T
SD
MemData
T
HD
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