Revision 1.09 - August 21, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Figure 10. DDR SDRAM Read Cycle Timing—Example
Oversampling Guard Band
DDR 1X Clock
DDR 2X Clock
Memclk (Diff.)
DQS at
MemCntl Pin
Data at Pin
D0
D2
D3
D4
D5
D6
D7
D8
D9
D1
Store 1st Data
in Stage 2
Feedback
Output
T1
T2
T3
T4
DDR 1X Clock cycle
Delayed DQS
Data Out Stage 1 (0)
Data Out Stage 1 (1)
Data out Stage 1 (2)
Valid
High
Low
D0
D1
D2
D3
Data Out Stage 2
PLB 1X Clock
64
AMCC Proprietary