Revision 1.09 - August 21, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Table 18. I/O Specifications—333 MHz to 667 MHz CPU
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
IOH
(minimum)
IOL
(minimum)
(TIS min)
(TIH min)
External Peripheral Interface
PerClk
11.08
11.08
11.08
11.08
11.08
11.08
na
7.37
7.37
7.37
7.37
7.37
7.37
na
PLB Clk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
1
PerAddr05:31
PerCS0:3
PerData00:31
PerDataPar0:3
PerOE
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PerReady
PerRW
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
11.08
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
7.37
PerWBE0:3
PerBLast
PerErr
ExtReset
BusReq
HoldReq
HoldAck
ExtAck
ExtReq
NFALE
NFCE0:3
NFCLE
NFData0:15
NFRdyBusy
NFREn
NFWEn
AMCC Proprietary
57
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
