Revision 1.09 - August 21, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Table 16. Peripheral Interface I/O Clock Timings
Clock
GMCTxClk frequency
GMCTxClk high time
GMCTxClk low time
GMCRxClk frequency
GMCRxClk high time
GMCRxClk low time
GMCGTxClk
Min
Max
Units
MHz
ns
125
125
45% of nominal
–
55% of nominal
–
ns
125
125
MHz
ns
45% of nominal
–
55% of nominal
–
ns
125
125
MHz
MHz
MHz
ns
GMCMDClk
2.5
25
GMCRefClk
125
125
GMCRefClk edge stability (phase jitter, cycle-to-cycle)
GMCRefClk rise time
GMCRefClk high time
GMCRefClk low time
GMCnRxClk
na
± 0.1
na
40% of nominal
60% of nominal
125
0.4
ns
–
ns
–
ns
125
125
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
GMCnTxClk
125
1000/(2TOPB1 + 2ns)
UARTSerClk
TmrClk
na
100
100
20
PerClk
TCK
na
57.97
100
USB2Clk (60MHz ± 0.05%)
PCIEnClkC, T (Differential clock input)
Notes:
60.03
250
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of the PLB clock. The
maximum OPB clock frequency is 100MHz.
AMCC Proprietary
53
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
