Revision 1.09 - August 21, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Table 17. I/O Specifications—All CPU Speeds (Sheet 1 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
IOH
(min)
IOL
(min)
(TIS min)
(TIH min)
PCI Express Interface
PCIEnATB
na
na
na
na
PCIEnRx
PCIEnRx
PCIEnTx
PCIEnTx
na
na
Ethernet GMII Interface
GMCCD
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
00
00
00
00
00
00
00
00
00
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
na
5.51
5.51
na
na
7.23
7.23
na
1
1
1
1
1
1
1
1
1
GMCCrS
GMCMDIO
GMCRxD0:7
GMCTxD0:7
GMCRxDV
GMCRxEr
5.51
na
7.23
na
na
na
GMCTxEr
5.51
5.51
7.23
7.23
GMCTxEn
Ethernet RGMII Interface (n = 0 or 1)
GMCMDIO
GMCnRxD0:3
GMCnRxCtl
GMCnTxD0:3
GMCnTxCtl
Internal Peripheral Interface
IICnSData
1
1
1
1
1
1
1
1
1
1
2.8
2.8
2.8
2.8
2.8
1.2
1.2
1.2
1.2
1.2
5.51
na
7.23
na
1
1
1
1
1
na
na
5.51
5.51
7.23
7.23
15.75
15.75
15.75
15.75
15.75
15.75
15.75
na
10.46
10.46
10.46
10.46
10.46
10.46
10.46
na
UARTnCTS
UARTnRTS
UARTnDSR
UARTnDCD
UARTnDTR
UARTnRI
UARTnRx
UARTnTx
15.75
na
10.46
na
SCPDI
SCPDO
15.75
15.75
15.75
15.75
15.75
10.46
10.46
10.46
10.46
10.46
USB2Data0:7
USB2Dir
4
4
4
4
0
0
0
0
5
5
5
5
2
2
2
2
USB2Next
USB2Stop
DMA Interface
DMAAck0:3
DMAReq0:3
DMAEOT0:3
Interrupts Interface
IRQ0:9
2.8
2.8
2.8
1
1
1
5.3
5.3
5.3
1.0
1.0
1.0
15.75
15.75
15.75
10.46
10.46
10.46
15.75
10.46
AMCC Proprietary
55
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
