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PPC405EX-NSB533TZ 参数 Datasheet PDF下载

PPC405EX-NSB533TZ图片预览
型号: PPC405EX-NSB533TZ
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA388, 27 X 27 MM, ROHS COMPLIANT, PLASTIC, MS-034C, EBGA-388]
分类和应用: 时钟外围集成电路
文件页数/大小: 71 页 / 1121 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.12 - Novenber 20, 2007  
PPC405EX – PowerPC 405EX Embedded Processor  
Preliminary Data Sheet  
The following diagram illustrates the relationship among the signals involved with a DDR write operation.  
Figure 9. DDR SDRAM Write Cycle Timing  
PLB Clk  
MemClkOut0  
T
SA  
Addr/Cmd  
T
DS  
T
HA  
T
DS  
DQS  
T
SD  
T
SD  
MemData  
T
HD  
T
HD  
T
= Setup time for address and command signals to MemClkOut0  
= Hold time for address and command signals from MemClkOut0  
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)  
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)  
= Delay from rising/falling edge of clock to the rising/falling edge of DQS  
SA  
T
HA  
SD  
HD  
T
T
T
DS  
Note: The timing data in the following tables is based on simulation runs using Einstimer.  
Table 21. I/O Timing—DDR SDRAM T  
DS  
Notes:  
1. All of the DQS signals are referenced to MemClkOut0 with the DQS delay line programmed to 1 cycle.  
2. Clock speed is 200MHz.  
TDS (ns)  
Signal Name  
Minimum  
Maximum  
DQS0  
DQS1  
DQS2  
DQS3  
DQS4  
4
4
4
4
4
6
6
6
6
6
AMCC Proprietary  
61