Revision 1.12 - Novenber 20, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Figure 10. DDR SDRAM Read Data Path for a Single Data Bit
FF: Flip-Flop
DDR 1X Clock
Ext FeedBack
Signals
Driver
MemFBD
FeedBack
Coarse Delay
Read Start
CAS Lat Delay
Signal Gen
DDR 1X Clock
Read Latency adjust circuit
Rec
Stage 2 Store
Oversampling
Fine Delay
MemFBR
Fine Delay
DQS aligned
Cycles
Delay
T1 T2 T3 T4
+1
feedback signal
(Guard Band)
Feedback
Data Capture
Window
On-time sample clock
Adjust
Oversampling
Clock
0
1
2
Q2_Ovs
3
Package
pins
0
2
FF
FF
Q3
Compare
FF
Q2
PLB bus
FF
(x64+ECC)
D
Read FIFO
Upper
[0:63]
Mux
C
Mux
DQS Rising
Edge Sync
Stage 1
MemData
Stage 2
Stage 3
Lower
(x32 bits +
x8 bits ECC)
FF
FF
FF
Q3
1
3
(x64+ECC)
Q2
PLB bus
[64:127]
FF
D
Mux
C
Mux
Programmed
Read DQS
Delay
DQS Falling
Edge Sync
DQS
(x4 + x1
ECC bits)
DDR 1X Clock
PLB 1X Clock
ECC detection and correction if enabled occurs after Stage 3 before completing the read on the PLB.
DDR SDRAM Read Cycle Timing
The following diagram illustrates the relationship of the signals involved with a DDR read operation.
Figure 11. DDR SDRAM Memory Data and DQS
DQS
T
SD
MemData
T
HD
64
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
