Revision 1.12 - Novenber 20, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
The feedback signal to the Feedback Data Capture Window is adjusted for propagation delay by the fine/coarse
delays and is automatically adjusted for variations in the DDR I/O due to supply voltage and temperature.
Compensation for driver/receiver variations is accomplished by driving and receiving the feedback signal on the
external MemFBD and MemFBR pins. Tuning the fine/coarse delays adjust for propagation delay. When properly
tuned, the feedback pulse is aligned to the first DQS in a four beat burst such that the rising edge of DQS is
nominally centered on the feedback pulse.
Software can adjust the pulse using the fine/coarse delays. Connection of MemFBD directly to MemFBR with the
minimum trace length is recommended.
The data captured in Stage 1 is relative to the DQS timing domain and is held for two DDR 1X cycles. Stage 2
samples the data in Stage 1 attempting to capture the first and/or second cycle of data in the DDR 1X domain. The
on-time-sample clock from the Stage 2 Store block samples the Stage 1 data at sample cycle T1, T2, T3 or T4. The
sample cycle is either selected by initialization software or can be automatically selected and adjusted by the DDR
controller. The Stage 1 data is sampled a second time by the over sample clock at a delayed sample point. The
delay between the on-time-sample and over sample clocks is the Over-Sampling-Guard-Band.
The feedback pulse is sampled with the data captured by the first DQS in the four beat burst. A match of one or
both of the sample clocks with the feedback pulse is a hit. The DDR controller based on hits or misses by the on-
time sample and over sample clocks adjust the sample cycle in order to track variations in DQS. Burst data from a
sample hit is passed to Stage 3.
In Stage 3 the data is synchronized to the PLB clock domain and eventually driven onto the PLB bus. The data
captured on the rising and falling DQS edges is unpacked into the correct bit locations on the upper (0:63) and
lower (64:127) PLB bus. When ECC is enable, ECC checking and corrections is done after Stage 3.
Figure 12 illustrates how the three Stage read logic captures the data in the DQS timing domain and synchronizes
it to the PLB clock domain. The first DQS of four beat burst is roughly centered on feedback signal pulse.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
